IRC logs for #openrisc Tuesday, 2016-03-15

--- Log opened Tue Mar 15 00:00:35 2016
olofkshorne: Bring it on. I haven't tried submitting it upstream. Just pushed it to our github repo02:40
shorneolofk: thanks, ill have a go05:11
shornestekern: I got a word back from my friend, he mentioned he would be able to sign your pgp key if required, but also give some other options05:12
stekernshorne: nice, appreciate it05:31
shornestekern: ill forward to you the details05:32
stekerngreat, thanks05:33
shornehope I am not making more work for you05:36
shornestekern: sent05:40
mithroHow would you explain why an open source CPU / instruction set is important in two sentences? (And thus why OpenRISC / RISC-V is awesome?)07:38
robtaylorOwn your platform.07:48
wallentoAn open source instruction set guarantees you it is free of licensing fees and that it will still be available in a few years07:54
wallentoolofk: ready for testing: https://github.com/wallento/verilator08:21
mwfcmithro: security needs trust anchors on the lowest level possible, most security cpus are heavily NDAed thus hard/impossible to verify.10:10
mwfcs/cpus/socs/10:11
shornewallento: I put something up with just a dump of my commands and some comments about what it does10:27
shornehttps://github.com/stffrdhrn/tutorials/blob/master/debugging/README.md10:27
shornefor debugging10:27
shorneI think it might need some more structure, but I think its helpful10:28
wallentocool, thanks!10:28
wallentoI can merge it and point to it from the tutorials10:28
wallentolike further reading10:28
shorneI'm open to any feedback10:28
wallentowill create a similar page for compiling code10:28
shorneI added a link to it in the tutorials/README.md10:28
shornenot sure if you wanted that10:29
wallentoyes, thats good10:29
wallentobut one proposal: rename debugging/README.md to docs/Debugging.md10:29
wallentothan we can add docs/CompilingBaremetal.md10:29
wallentoetc.10:29
wallentodoes that make sense?10:30
shornesure, I was just copying the structure of de0_nano10:31
shorneI guess thats different10:31
shorneill move now10:31
wallentoyes, that would be the actual tutorials for the boards that also contain code10:31
wallentoand some extra documentation in docs10:32
wallentothanks, please create a PR or push yourself10:32
wallentoI added you to openrisc/tutorials10:32
shorneyeah, Ill do PR since others might want to review , but if no reviews you or I can merge10:33
_franck__shorne:  speicify <- typo10:34
wallentookay, great, thanks10:35
shorne_franck__: I think I fixed it just now during proof reading checking again10:43
shorneit was there a few times10:44
shorneshould be fixed now10:53
shornetime for bed10:59
olofkwallento: Just remembered that I wrote some information for when I did the MyriadRF Stream board. Might be stuff there worth copying into the tutorials11:19
wallentoolofk: cool, is it on your blog?11:19
olofkhttps://github.com/myriadrf/STREAM11:20
olofkhttps://github.com/myriadrf/STREAM/tree/master/docs11:20
olofkIt's in asciidoc though11:21
olofkno wait11:21
olofkhttps://github.com/myriadrf/STREAM/tree/master/stream_openrisc_soc/doc11:21
olofkThey decided to put everything in one big fat repo11:22
olofkIs it possible to view html files on github?11:22
wallentounfortunately not11:23
wallentoonly via github pages11:23
olofkah ok. My docs are asciidoc/html, so it's a bit awkward to view them on github11:24
olofkshorne: Thanks for the patch. Are you around for some comments?11:25
olofkshorne: Oh, I guess not. Unless you sleep for less than 30 minutes :)11:27
wallentoas he lives in japan, he has probably adopted already. He meant time for some sleep standing in the subway ;)11:28
olofkHaha. Anyway. Patch is fine, but I'd like to take the opportunity to replace the verilog section with filesets instead11:32
olofkFuck it. I'll apply it as is and just change it afterwards11:57
olofkwallento: Your verilator patch works fine!12:20
olofkJust did a quick test, but no problem with tha12:21
olofkt12:21
olofkWorking on packaging the pulpino stuff too. They got a ton of cores in there12:58
robtaylorolofk: nice :)13:09
robtaylorolofk: tweet it ;)13:09
olofkrobtaylor: Haha. Already did a few weeks ago. Will do it again when I get it running. I'm pretty close now13:15
wallentoolofk: nice!14:09
wallentoolofk: anyone working on vivado support for fusesoc?14:09
wallentoplan to add support for the Nexys4 board14:09
olofkwallento: That would be great. I actually started with that just a few days ago, but didn't get very far15:52
olofkI think I managed to run a program on pulpino with modelsim now15:52
olofkThere is an insane amount of CMake stuff in the pulpino repo. Time to replace some of it with FuseSoC now15:54
olofkWhat's the status of gdbserver for OpenRISC?16:38
olofkwallento: I pushed a patch to tutorials17:33
olofkand one more17:53
shorneolofk: thanks for the fixes, I just copied the .core from the old wb_sdram_ctrl core. I didnt know about the new filesets. Now I se18:05
shornenow I de18:05
shornenow I *do*18:07
olofk:)18:22
olofkYeah, there isn't very much documentation for FuseSoC18:22
olofkBut at least I started to put up some stuff on my blog http://olofkindgren.blogspot.com/18:23
olofkAnd thanks again for the patches18:23
olofkoh great. Did ORSoC drop the OpenRISC bug tracker on opencores?18:52
andrzejrwallento, I'd be interested in Nexys4 board support. Got it (partially) working here but run out of time.22:11
andrzejr(the Nexys4DDR version)22:11
andrzejrI've pushed accumulated changes to https://github.com/andrzej-r/orpsoc-cores/tree/nexys4ddr22:37
andrzejrETH, VGA not working, I suspect low memory bandwidth22:38
andrzejrDDR controller only works with bursts disabled and only can access half of the DRAM memory.22:39
andrzejrLinux and BareBox boot, openocd works with on-board JTAG tap.22:41
andrzejrUse https://github.com/andrzej-r/fusesoc/tree/andrzej-r to build it (some features were merged in fusesoc but Nexys4DDR may still need this branch)22:52
--- Log closed Wed Mar 16 00:00:36 2016

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