| --- Log opened Sat May 28 00:00:26 2016 | ||
| olofk | shorne_: Good find. And strange behaviour | 03:16 |
|---|---|---|
| olofk | Sorry that I haven't gotten back to your pull request. I'll try to do that today | 03:16 |
| shorne_ | olofk: in the end I got it to be able to find gcc with some hacks. But it tries to mmap the code into the host but it seems thats only available on linux. So probably we dont want to support compile for now. | 05:09 |
| olofk | shorne_: Fair enough. | 06:46 |
| wallento | shorne_: I pulled your request | 06:55 |
| wallento | sorry I was always thinking it will be amended with further fixes :) | 06:56 |
| wallento | thanks a lot, I very much appreciate your hard efforts! | 06:56 |
| olofk | wallento: There's a lot of merges in the tree now. Should we untangle this a bit before pushing upstream? | 06:56 |
| olofk | shorne_: I think you need to sign the fsf copyright paper also before we can push this upstream | 06:57 |
| olofk | Haven't done it myself, but there are plenty of other people here who knows what should be done | 06:57 |
| wallento | olofk: yes of course | 06:57 |
| wallento | we should rebase onto a single update | 06:57 |
| wallento | or a few | 06:57 |
| wallento | we did it with newlib too | 06:58 |
| olofk | ah ok. | 06:58 |
| wallento | you just need to do a git diff master or1k from time to time | 06:58 |
| wallento | to be really sure :) | 06:58 |
| olofk | How does this travis integration on github work? Can I just add a .travis.yml to my repo, or do I need to register somewhere and let travis know that my project exists? | 07:40 |
| wallento | olofk: you need to register | 08:02 |
| wallento | at travis-ci.org | 08:02 |
| wallento | Then browse your repos and those of the orgs | 08:03 |
| wallento | and turn it on | 08:03 |
| wallento | then in the settings you should turn on "only build when .travis.yml is present" | 08:03 |
| wallento | thats it | 08:03 |
| wallento | I think you can register with Github OAuth | 08:04 |
| wallento | yes, its Github authentication | 08:04 |
| bandvig | I've got a question which is regard to interaction DU and other CPU modules. | 09:43 |
| bandvig | In particular. Could I made assumption that pipeline have to be stalled (by DU command) before DU-reading various SPR and GPR? | 09:43 |
| tariq786 | hi There. I have a couple of basic questions for anyone to answer | 12:57 |
| tariq786 | Q1) What is the difference between OpenRISC and OpenRISC Soc? | 12:59 |
| tariq786 | or between OR1200 and ORPSOC? | 12:59 |
| GeneralStupid | hi | 13:02 |
| GeneralStupid | i hope i'll tell you the right things. | 13:02 |
| tariq786 | GeneralStupid: Please go ahead | 13:02 |
| GeneralStupid | OpenRISC is a Processor Architecture | 13:02 |
| GeneralStupid | an OpenRISC SoC is a Processor which can be actually used (because it will need things like the wishbone bus for example. The SoC is a complete processor with an OpenRISC Core) | 13:03 |
| GeneralStupid | OR1200 is one openrisc implementation, like mor1kx | 13:03 |
| GeneralStupid | ORPSOC is the reference plattform (the reference openrisc SoC) | 13:04 |
| tariq786 | GeneralStupid: When you say processor architecture, does it mean only ALU and Control logic? | 13:05 |
| tariq786 | GeneralStupid: When you say SOC, it is ALU + control logic + peripherals? Am i correct? | 13:06 |
| tariq786 | ? | 13:10 |
| GeneralStupid | https://wiki.myriadrf.org/images/thumb/b/b5/STREAM-OpenRISC-Block-Diagram.png/550px-STREAM-OpenRISC-Block-Diagram.png | 13:11 |
| GeneralStupid | i had some very nice documentation with nice diagrams ... but i dont find it right now | 13:12 |
| GeneralStupid | if you want to start i would recommend fusesoc to you | 13:13 |
| tariq786 | where is fusesoc? | 13:13 |
| tariq786 | GeneralStupid: Please correct my statements in green above if you think they are wrong | 13:14 |
| GeneralStupid | tariq786: i would say your right. | 13:14 |
| GeneralStupid | http://opencores.org/or1k/ORPSoC | 13:14 |
| tariq786 | GeneralStupid: I have seen somewhere people are running linux on top of OpenRISC. Is that possible? | 13:15 |
| tariq786 | GeneralStupid: is it OpenRISC or ORPSOC? | 13:16 |
| GeneralStupid | i think you can say openrisc | 13:18 |
| GeneralStupid | yes it is possivle | 13:18 |
| GeneralStupid | µClinux afaik | 13:18 |
| tariq786 | GeneralStupid: what make is possible to run linux on openrisc? | 13:19 |
| GeneralStupid | what do you mean? | 13:19 |
| GeneralStupid | https://github.com/embecosm/chiphack/wiki/OpenRISC-SoC-Practical-Session-Instructions | 13:20 |
| tariq786 | GeneralStupid: it is hard to sink in somehow :( | 13:21 |
| tariq786 | GeneralStupid: So lets go thru this thought process | 13:22 |
| tariq786 | GeneralStupid: what makes intel or AMD run linux | 13:22 |
| tariq786 | GeneralStupid: Linux can be thought of as list of instructions and openRisc can be thought of as a processor that can execute that instructions | 13:23 |
| tariq786 | GeneralStupid: does this analogy makes sense? or is incomplete or bogus? | 13:23 |
| tariq786 | ?? | 13:35 |
| GeneralStupid | linux is a list of instructions | 14:15 |
| GeneralStupid | at last every program or software you run is "just" a list of instructions. An Operating System, too | 14:16 |
| GeneralStupid | but that is not something which is particular with openrisc | 14:16 |
| olofk | tariq786, GeneralStupid : A few corrections and clarifications | 15:09 |
| olofk | When we talk about OpenRISC we often mean "OpenRISC 1000", which is the specification | 15:10 |
| olofk | The specification describes what each CPU instruction does and similar things | 15:10 |
| GeneralStupid | olofk: i thoight openrisct would be the specification | 15:12 |
| olofk | To give a comparasion, x86 is another specification. There are tons of different CPUs (Intel Celeron, Atom, Core etc as well as CPUs from AMD, Cyrix and VIA) that all implement the x86 specification | 15:13 |
| olofk | You can find the specification here https://github.com/openrisc/doc | 15:13 |
| olofk | Then we have the processor implementations, the actual CPU cores that implement the spec | 15:14 |
| olofk | The original one was called or1200, but the one we mostly use nowadays is called mor1kx. There are also other implementations such as altor32, or10n and other | 15:14 |
| olofk | There is also a javascript implementation (jor1k.com) that implements openrisc 1000 (or or1k as we call it), and a C simulator called or1ksim | 15:15 |
| olofk | Then we have the SoC part | 15:16 |
| olofk | Desktop CPUs still mostly have the CPU in a separate chip and then external chips for networking, usb, graphics and so on | 15:16 |
| olofk | But in the embedded space (cell phones, appliances etc) this is usually all built into a single chip | 15:17 |
| olofk | Hence the System on Chip (SoC) | 15:17 |
| tariq786 | olofk: Please excuse my ignorance. But i hope i can learn from you and then educate others | 15:17 |
| tariq786 | olofk: Thanks for the explanation | 15:18 |
| olofk | We can put whatever we want in the chip, but early in OpenRISC development there was something called ORPSoC which was then OpenRISC Reference System on Chip | 15:18 |
| olofk | tariq786: No worrries. Happy to explain | 15:18 |
| tariq786 | olofk: what is current ORPSoC called? | 15:18 |
| olofk | ORPSoC consisted of the or1200 CPU + some chosen peripheral controllers such as a UART, memory controller and basic stuff | 15:18 |
| tariq786 | olofk: It seems it was similar to Amber http://opencores.org/project,amber. Correct me if i am wrong | 15:19 |
| olofk | tariq786: juliusb created orpsoc version 2 some years ago, and I started doing ORPSoCv3 some time later | 15:19 |
| olofk | But both of these projects are dead now | 15:19 |
| tariq786 | olofk: why? | 15:19 |
| olofk | Even though orpsocv2 is still used | 15:19 |
| olofk | Because I created something called FuseSoC instead | 15:20 |
| tariq786 | olofk: great. Why did you create this instead of Orpsoc3 | 15:20 |
| olofk | FuseSoC is created from a need that we saw in the OpenRISC community, but it has no dependency on OpenRISC. Therefore I didn't want OpenRISC in the name | 15:21 |
| tariq786 | olofk: did you create an RISC implementation from the scratch for fuseSoC? | 15:21 |
| olofk | I did it because I saw that I could use the FuseSoC project for all kinds of FPGA development, even though it didn't contain a CPU | 15:21 |
| olofk | tariq786: No, neither FuseSoC nor ORPSoC has no real RTL code. It's just systems to bind together cores and create a SoC | 15:22 |
| tariq786 | olofk: should n't SoC have a CPU such as OpenRISC? | 15:23 |
| olofk | So FuseSoC is basically a package manager | 15:23 |
| olofk | Well, I guess that most things that are called a SoC has a CPU inside, but there are plenty of other chips that has no CPU | 15:24 |
| olofk | So to wrap it up, we now use FuseSoC to help us put together SoCs with OpenRISC and a bunch of peripherals | 15:24 |
| olofk | oh, and I draw that diagram you posted before :) | 15:24 |
| olofk | From myriadrf | 15:24 |
| olofk | gtg | 15:24 |
| tariq786 | olofk: please give examples of soc without cpu | 15:24 |
| tariq786 | thats the last question | 15:25 |
| tariq786 | ok later when you have time | 15:25 |
| tariq786 | olofk: I want to contribute to this open source work. How may i get started? | 15:25 |
| tariq786 | Anyone here to answer a few more questions? | 16:28 |
| tariq786 | What is the minimum RTL required to boot linux? | 17:07 |
| tariq786 | Can a single cycle (unpipelined) ALU + Control logic in RTL meet this requirement? I hope not? | 17:09 |
| tariq786 | If not, what are the essential components needed to boot linux off RTL? thanks for your patience | 17:09 |
| olofk | tariq786: Starting with your last question, we have SoCs based on both mor1kx and or1200 that can boot Linux on several different FPGA boards | 17:11 |
| olofk | The absolute minimum components you need are a CPU and a memory controller | 17:11 |
| olofk | You probably won't get far without a UART as well | 17:12 |
| olofk | Do you have an FPGA board? | 17:12 |
| tariq786 | olofk: yes, digilentinc's SPartan 6 | 17:12 |
| olofk | tariq786: Hmm... which one? Atlys, LX9 Microboard? | 17:13 |
| olofk | Nexys3? | 17:13 |
| olofk | Anvyl? | 17:13 |
| olofk | They got several Spartan6-based boards :) | 17:14 |
| tariq786 | hang on a minute | 17:14 |
| olofk | http://store.digilentinc.com/fpga-programmable-logic/by-technology/xilinx-spartan-family/ | 17:14 |
| tariq786 | http://store.digilentinc.com/atlys-spartan-6-fpga-trainer-board-limited-time-see-nexys-video/ | 17:15 |
| GeneralStupid | whats about a de0 nano? | 17:15 |
| GeneralStupid | its pretty cheap | 17:15 |
| tariq786 | I already have digilent's spartan 6 | 17:16 |
| olofk | tariq786: Well then, you're in luck. We have a SoC implementation already for Atlys | 17:16 |
| tariq786 | Olofk: Why i am going through this pain is so that i can contribute like you guys are doing. I am very much open source | 17:16 |
| olofk | tariq786: We're happy to help out | 17:17 |
| tariq786 | here is a snapshot of my 2 cents | 17:17 |
| tariq786 | https://docs.google.com/document/d/1PSjfm6eS0B3UUPJmPf7PH0tNsF7ZFKIKfPldmF3ucKY/edit | 17:17 |
| tariq786 | olofk: I don't have large scale or system level experience. That is why i am struggling with growing pains | 17:18 |
| tariq786 | olofk: and i thought to ask you for help | 17:19 |
| tariq786 | olofk: Here are a few more | 17:19 |
| tariq786 | https://bitbucket.org/tariq786/packetizer | 17:20 |
| tariq786 | <tariq786> https://github.com/tariq786/unambiguous-encapsulation | 17:20 |
| tariq786 | <tariq786> http://opencores.org/project,gcm-aes | 17:20 |
| tariq786 | <tariq786> http://opencores.org/project,aes-encryption | 17:20 |
| tariq786 | <tariq786> http://people.umass.edu/tbashira/OCB3.htm | 17:20 |
| tariq786 | olofk: Here is the board that i have | 17:22 |
| tariq786 | http://www.xilinx.com/support/documentation/university/XUP%20Boards/XUPAtlys/documentation/Atlys_rm.pdf | 17:22 |
| olofk | tariq786: So, these are cores that you have already done? | 17:22 |
| tariq786 | olofk: yes | 17:22 |
| olofk | Cool | 17:22 |
| tariq786 | olofk: but you see, its not large scale or system level as i said earlier | 17:22 |
| tariq786 | that is why i consider it only a small contribution | 17:23 |
| olofk | tariq786: That's fine, and I think FuseSoC can be helpful here | 17:23 |
| olofk | What I want to do with FuseSoC is to create a large library of components that can be used by different implementations | 17:23 |
| tariq786 | olofk: please explain more | 17:24 |
| olofk | There are already ~100 cores available in the standard FuseSoC library | 17:24 |
| tariq786 | can you give me a link so i can take a look at these 100 cores | 17:24 |
| olofk | tariq786: You have any experience with software package management, such as rpm or deb packages? | 17:24 |
| olofk | https://github.com/openrisc/orpsoc-cores | 17:24 |
| tariq786 | olofk: I have used them to install on Ubuntu and Fedora systems. Thats what i know | 17:25 |
| olofk | tariq786: Well, think of FuseSoC as the equivalent, but for VHDL/verilog code. Instead of putting all your code in a single repository, you can more easily reuse existing code and only have what's unique for your project | 17:27 |
| olofk | So you create a package description for your gcm-aes core, and other projects can depend on that | 17:27 |
| olofk | Or for your HDMI2Ethernet project, you can separate it into different cores, and then have a top-level project that depends on all the other parts | 17:28 |
| olofk | That way other projects can also use the subcomponents | 17:28 |
| tariq786 | olofk: that is more like coregen in Xilinx? | 17:29 |
| olofk | tariq786: Yes, partly | 17:29 |
| tariq786 | olofk: partly? | 17:29 |
| olofk | Coregen is only for Xilinx cores. FuseSoC currently handles Altera Quartus, Xilinx ISE and IceStorm for building FPGA binaries | 17:30 |
| olofk | Coregen also doesn't handle dependencies | 17:31 |
| olofk | And with FuseSoC, you can run your testbenches in different simulators | 17:31 |
| tariq786 | olofk: is there a good time to discuss in detail tomorrow? | 17:32 |
| tariq786 | olofk: How can i use my Atlys board to play with FuseSoC? | 17:33 |
| tariq786 | gtg but catch you later | 17:34 |
| olofk | tariq786: Not sure how much I'll be around tomorrow | 17:34 |
| olofk | But get fusesoc from https://github.com/olofk/fusesoc | 17:35 |
| olofk | Install it and run "fusesoc build atlys" to generate a OpenRISC SoC for your board | 17:35 |
| olofk | tariq786: FYI, I just now created a basic core file for your gcm_aes project, so you can simulate it in FuseSoC | 17:39 |
| olofk | Just to get you an idea of how to make a core FuseSoC-compatible | 17:41 |
| olofk | Just tested it with four different simulators. Testbench seems to run fine in all of them, but it seems like I'm missing some exit criteria | 17:43 |
| ZipCPU|Laptop | olofk: I am currently in the process of building an SD-Card controller that will work with a SPI interface, as opposed to the normal SD interface. | 17:43 |
| ZipCPU|Laptop | Is there anything special that I will need to do in order to make it FuseSoC compatible? | 17:44 |
| olofk | tariq786: This is what it looks lik http://255a5568504b80bc.paste.se/ | 17:44 |
| olofk | ZipCPU|Laptop: Just out of curiosity, why not reuse an existing one? | 17:45 |
| ZipCPU|Laptop | Well ... for a couple of reasons, but one of them was that the SD-Card controller I found on open cores only worked for SD mode, not SPI mode. | 17:46 |
| olofk | But for your question, no, FuseSoC is designed to not put any requirements on cores | 17:46 |
| olofk | There are some things you can do to better integrate with FuseSoC, but no formal requirements | 17:46 |
| ZipCPU|Laptop | Is there a public repository requirement? OpenCores vs github? Or ... is there a FuseSoC config file that should be included with the core? | 17:47 |
| olofk | For example, if you use the vlog_tb_utils core in your testbench, you will automatically get command-line switches for breaking the simulation after a certain time, optional VCD generation, heartbeat monitor and things like that | 17:47 |
| ZipCPU|Laptop | Wow ... that's a lot. Is this documented anywhere? | 17:48 |
| olofk | ZipCPU|Laptop: Not even that :) There are currently backends to handle cores from opencores, github, zip/tar.gz files or general git repos | 17:48 |
| olofk | And you don't have to put the .core file in your repo | 17:48 |
| ZipCPU|Laptop | But ... wouldn't it make sense to place the .core file into the repo to facilitate FuseSoC integration? | 17:48 |
| olofk | Most cores have the .core file in the FuseSoC standard library, with just a section called [provider] to tell FuseSoC where to find it | 17:49 |
| olofk | ZipCPU|Laptop: Yes and no. FuseSoC still needs to know where to find the cores, and I did it this way also so that I could add cores to the library without forcing the author to add a file | 17:49 |
| olofk | Because frankly, it's hard form me to convice people to add some configuration file for their pet project | 17:50 |
| ZipCPU|Laptop | That makes sense. | 17:50 |
| olofk | ZipCPU|Laptop: Unfortunately there is extremely little documentation | 17:51 |
| olofk | But if you run one of the better supported cores, like say, mor1kx-generic, you can run "fusesoc sim mor1kx-generic --help" to get a list of the switches for that system | 17:51 |
| ZipCPU|Laptop | Okay, well ... perhaps the code is self-documenting ;) Is the FuseSoC code easily found? | 17:52 |
| olofk | Each core can register new command-line switches themselves. These are then translated to a top-level generic/parameter, a verilog plusargs or sent directly to the tool | 17:52 |
| olofk | The code is here https://github.com/olofk/fusesoc | 17:52 |
| olofk | It's not self-explaining, and I'm ashamed of the lack of documentation | 17:52 |
| olofk | I've tried to write some topic posts on my blog. You might find some clues there | 17:53 |
| olofk | http://olofkindgren.blogspot.com/ | 17:53 |
| ZipCPU|Laptop | I noticed a "doc" directory in your repo. Is it worth much? | 17:53 |
| olofk | Not that much. Most of it consists of the available sections and options you can put in your .core file | 17:54 |
| ZipCPU|Laptop | And the orpsoc-cores directory contains examples of cores that use FuseSoC? | 17:55 |
| olofk | ZipCPU|Laptop: Correct. I intend to rename it some day, but I usually refer to it as the "FuseSoC standard library" | 17:55 |
| olofk | It's a remain from the early days of development when it was still called orpsocv3 | 17:56 |
| olofk | Before I realized that there wasn't a single OpenRISC-specific line of code in the project :) | 17:56 |
| olofk | Even though many of the cores themselves still are OpenRISC-related | 17:56 |
| ZipCPU|Laptop | Does it contain an SD card controller that works in SPI mode? :? | 17:56 |
| olofk | haha | 17:56 |
| olofk | I only added the one from OpenCores | 17:56 |
| olofk | But! | 17:56 |
| ZipCPU|Laptop | I'll take that as a "no." | 17:57 |
| olofk | Google did a prototype of their ProjectVault that they showed at last year's Google I/O conference | 17:57 |
| olofk | Their prototype used OpenRISC and was created with FuseSoC. I think that contains a SD card controller. You could check that out | 17:58 |
| olofk | Oh... and I created .core files for the Pulpino project from ETH Zurich. There should be an SD card controller there I think | 17:58 |
| olofk | Ahh. no. Sorry. That was a quad SPI one | 17:59 |
| olofk | Oh.. but wait. stekern did a FuseSoC port of the minimig amiga emulator. That one most definitely uses an SPI controller to talk to the SD Cards | 17:59 |
| olofk | https://github.com/skristiansson/minimig-de1 | 18:00 |
| olofk | Doesn't look like he wrote any .core files for it though (or did you, stekern?), but that's quickly done | 18:01 |
| ZipCPU|Laptop | Looks like I've got some more research/work to do. Thanks for the tips. | 18:01 |
| olofk | oh well. Time to sleep now. Happy to help out if you need any help. FuseSoC-related or not | 18:02 |
| ZipCPU|Laptop | (I've actually got the core written, just not working yet. You know ... the first 5% of the work ;) ) | 18:02 |
| shorne | olofk: I'll look into signing, but I guess it pulls in a lot of fixes over the years (mainly peter's) I guess he must have signed. | 19:40 |
| shorne | As per the patch to upstream, I think we need to separate out/remove the or1ksim lib stuff (we can use remote target anyway to run on or1ksim). I guess since jeremybennett wrote the or1ksim target I would like to get his ok. | 19:43 |
| shorne | wallento: I guess there might be a few more patches. We will need to squash actual upstream patch into a few large patches | 19:52 |
| shorne | olofk: FYI, some docs are here, https://gcc.gnu.org/contribute.html Not sure if my work so far is (significant) | 19:55 |
| shorne | It looks liek the request for papers will be initialized once we submit to the gnu project maintainers (i.e. gdb maintainers) | 19:59 |
| -!- Shentino2 is now known as Shentino | 22:43 | |
| --- Log closed Sun May 29 00:00:28 2016 | ||
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