--- Log opened Sat Mar 26 00:00:52 2016 | ||
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GeneralStupid | hey, anyone saw that fusesoc "issue" ? | 12:47 |
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GeneralStupid | i wont reply for that. I needed that too and i just copied the Board directory... (yes, thats a really nice approach) | 12:49 |
wallento | yes, I wrote it | 13:44 |
wallento | I am not sure if there is a good idea for that | 13:45 |
wallento | olofk: saw your tweet regarding system verilog | 13:58 |
wallento | which tools do you have problems with? | 13:58 |
wallento | I exchanged a few mails with Andreas from Pulpino and Wei from lowRISC to find best practices | 13:59 |
wallento | we still need to put the summary somewhere | 13:59 |
wallento | the most stupid tool is XSIM | 14:01 |
wallento | this is a blocker for all interfaces stuff | 14:01 |
wallento | because if you connect through an interface it usually selects a random one of that type from somewhere in your system.. | 14:01 |
olofk | wallento: icarus didn't handle always_comb, class and several other things I can't remember now | 18:01 |
olofk | xsim just gives me a cryptic error now | 18:03 |
olofk | verilator might actually be quite close. Now I get some kind of width error in one place that I don't understand | 18:04 |
olofk | I have hacked quite a lot in some of the files to work around some of the basic issues | 18:05 |
olofk | For example, I have removed the riscv_tracer, since none of the tools liked that one very much :) | 18:05 |
olofk | And I removed all asserts to make verilator happy | 18:06 |
olofk | And replaced some of the always_comb with simplified constructs to make icarus happy.. until I realized that it wouldn't parse the other code anyway | 18:06 |
olofk | And of course I had to remove the VHDL uart | 18:07 |
olofk | I give up now. No idea how many errors left to fix for verilator support | 18:17 |
olofk | But I think that pulpino would be a nice target for verilator | 18:17 |
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--- Log closed Sun Mar 27 00:00:53 2016 |
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