| --- Log opened Thu Nov 12 00:00:06 2015 | ||
| olofk | Has anyone used geekbooks.me ? | 09:51 |
|---|---|---|
| hesham | olofk: So picorv32 is working now, that's great! Would you like to try out the srec bootloader there? | 10:06 |
| olofk | hesham: Yeah. I fixed the elf-loader to handle little endian as well | 10:07 |
| olofk | There's no UART on the picorv32 system, so I can't test the srec stuff | 10:07 |
| hesham | Is not it working with other open cores like mor1kx? | 10:08 |
| hesham | And how can I run/test it? | 10:08 |
| hesham | If you're interested I can work on getting my vscale work integrated. But they the code is not very mature yet. | 10:09 |
| olofk | hesham: Ah, you wrote it in C? | 10:09 |
| hesham | No assembly | 10:10 |
| hesham | It's initializing the UART core, and just getting ascii srec file from PC, and jump to 0x200 | 10:10 |
| olofk | Then it should work for the OpenRISC stuff too. Want to try it, but haven't got time right now. Is it small enough to fit into a boot ROM | 10:10 |
| olofk | ? | 10:10 |
| olofk | And I would love to see your vscale stuff integrated, but no stress | 10:11 |
| hesham | It won't work with OpenRISC because I wrote it in RISC-V assembly | 10:11 |
| olofk | aha. I got you wrong then | 10:12 |
| hesham | So if I want to add the vscale stuff, would it be a new "systems/riscv" or a separate core? | 10:12 |
| hesham | with definitions at orpsoc-defines.v? | 10:12 |
| olofk | I think it's better to use a new core. | 10:12 |
| olofk | Hopefully it will get a little easier to build new systems in the future, so we don't have to mess with `ifdefs | 10:13 |
| hesham | Ah, OK, I will try to add support to refer to my vscale repo like picorv32 | 10:14 |
| hesham | The bootloader is currently about 250 words | 10:14 |
| hesham | 32-bit words, but it's not optimized at all. | 10:15 |
| olofk | 250 words is ok. I still thought it was written in C when I asked about the size | 10:21 |
| olofk | hesham: If you're not ready to integrate vscale into orpsoc-cores, you can put a .core file in your repo, and I can just clone it and add it to the library path to test it | 10:22 |
| olofk | Do you have it in a public repo already? | 10:22 |
| hesham | olofk: Yes https://github.com/heshamelmatary/wb_riscvscale | 10:24 |
| hesham | I would see what you did with picorv32, and try to imitate it there. And maybe add support for an entire system to be built from FuseSoC like with mor1kx-generic | 10:26 |
| olofk | hesham: Cool. I'll take a look when I get some time | 11:27 |
| hesham | olofk: OK, I've sometime today, so I'll try to add the support to my repos, and maybe push pull requests later. | 11:29 |
| olofk | hesham: Cool! | 11:33 |
| olofk | hesham: I started adding support for simulating the upstream vscale | 13:15 |
| olofk | Seems like it runs fine in icarus with my first test case at least | 13:15 |
| hesham | olofk: Great. Should I hold off my "systems/vscale-generic" addition? | 13:16 |
| olofk | hesham: It would be great to have a SoC built around vscale. I have just added stuff to simulate the CPU core | 13:18 |
| hesham | Ok perfect. I'll test it. It boots from 0xf0000000 BTW. | 13:20 |
| olofk | Thanks. I might need some help | 13:23 |
| olofk | hesham: Do you have any elf files I can use to test it? There's only hex files in the vscale repo, and I would like to change it to use the elf-loader instead | 13:24 |
| hesham | I have the bootloader for Icarus that just jumps to 0x200 as RISC-V expects | 13:25 |
| hesham | Currently I'm using hello world, but this will need UART | 13:25 |
| hesham | I can write/compile an elf program for you, just let me know what do you need from it. | 13:25 |
| olofk | hesham: Great. I'll ping you when I need an elf | 14:01 |
| hesham | olofk: I submitted a pull request for a vscale-generic SoC that runs hello world | 14:13 |
| hesham | olofk: and sent you an e-mail with a hello world elf file to test with. | 14:29 |
| olofk | Thanks hesham. I pulled the wb_riscvscale patch and commented on the other one | 14:43 |
| hesham | olofk: Thanks for the comments. I am working on them now | 14:55 |
| hesham | I get an error when changing orpsoc_tb.v to vscale_tb.v | 14:56 |
| hesham | "error: Unable to find the root module "orpsoc_tb" in the Verilog source." | 14:56 |
| hesham | wb_intercon assumes orpsoc_tb | 14:56 |
| olofk | hesham: Ah... that's not very well documented, and a bit hacky | 15:11 |
| olofk | You need to add a section called [simulator] and add a entry "toplevel = name_of_toplevel_module" | 15:12 |
| hesham | So should I keep it orpsoc_tb for now? | 15:12 |
| hesham | Ah, that better | 15:12 |
| hesham | that's* | 15:12 |
| olofk | Like this https://github.com/openrisc/orpsoc-cores/blob/master/cores/stream_utils/stream_utils-1.0.core#L23 | 15:13 |
| olofk | Actually, I think you can also run with --testbench=name_of_module | 15:13 |
| hesham | olofk: "error: Unable to find the root module "bench/verilog/vscale_tb.v" in the Verilog source." | 15:36 |
| hesham | Although it's there. | 15:37 |
| hesham | Ah sorry, I should provide the module name not the file | 15:37 |
| hesham | It works now | 15:37 |
| hesham | olofk: Check the pull request again please. I've addressed all your comments (I hope). | 16:52 |
| olofk | Anyone with vivado 2015.1 who can check if the clog2 bug is there? | 22:21 |
| --- Log closed Fri Nov 13 00:00:07 2015 | ||
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