| --- Log opened Mon Aug 17 00:00:03 2015 | ||
| andrzejr | olofk, axi4-lite is very popular. That's hard to underestimate - all the work I've just put into writing a WB<->DRAM adapter wouldn't be needed at all. | 00:21 |
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| olofk | andrzejr: blueCmd did a WB<->AXI4-lite adapter a while ago https://github.com/bluecmd/wb-axi | 05:35 |
| olofk | And I agree that the AXI4 family probably is the way to go. One potential issue however is that the license status isn't very clear. I've been trying to get a definite answer to how it's allowed to be used, but I'm not quite sure yet | 05:37 |
| olofk | lowRISC avoided using AXI4 partly because of that | 05:38 |
| andrzejr | olofk, there are 4 issues: | 07:27 |
| andrzejr | (1) political - using the bus is supporting ARM and their licensing policy, IMHO this is the most important. | 07:27 |
| andrzejr | (2) trademarks - usually not enforced if properly attributed and if no compatibility is claimed, but if in doubt we may simply delete all references to "AXI" in documentation and code. | 07:28 |
| andrzejr | (3) copyright - this is only relevant to specification. We should not use the specification or claim compatibility with it. | 07:29 |
| andrzejr | (4) patents - always a potential problem but that's why I am mentioning axi4-lite - there are no novel solutions in it. If they are, they also apply to any similar custom solution we may create. | 07:31 |
| andrzejr | BTW, what bus low-RISC is using? | 07:34 |
| olofk | andrzejr: Agree with all four points. I do think however that axi4-lite isn't the best bus for high-throughput buses | 07:44 |
| olofk | They are using a few different buses IIRC, but the one I'm thinking about is called TileLink. It's a cache-coherent thing developed at Berkeley | 07:44 |
| olofk | So perhaps the biggest reason for not using AXI4 might actually be NIH ;) | 07:45 |
| olofk | I was supposed to mentor a GSoC project this year for a TileLink <-> Wishbone bridge actually. Unfortunately lowRISC didn't get enough slots as well as me realizing I didn't have enough time to spend on that | 07:47 |
| andrzejr | I was just trying to google some information about TileLink, the link to specification is dead though | 07:47 |
| andrzejr | https://github.com/ucb-bar/uncore/blob/master/doc/TileLink0.3.1Specification.pdf | 07:47 |
| olofk | But I think that they decided to fund a student implementing the bridge outside of GSoC | 07:47 |
| olofk | Yes. The details are a bit sparse | 07:47 |
| olofk | At least they were when I looked at it last | 07:47 |
| olofk | oh, the link is broken | 07:48 |
| olofk | https://docs.google.com/document/d/1Iczcjigc-LUi8QmDPwnAu1kH4Rrt6Kqi1_EUaCrfrk8/pub | 07:48 |
| olofk | Still not terribly detailed | 07:49 |
| andrzejr | We could simply use whatever they use. I assume they came up with this solution because they hit the same problem as we did. | 07:53 |
| andrzejr | what is the performance problem with axi4-lite you were referring to? just so that I know what to avoid | 07:55 |
| olofk | There's no burst mode in AXI4-Lite. I'm actually not sure however if that's necessarily a problem as long as you can queue up transactions efficiently | 07:56 |
| olofk | And I think it's defined strictly as 32-bit which might be an issue if we want really wide buses to main memory | 07:57 |
| olofk | I can see two drawbacks with TileLink. 1. Implementation complexity (probably overkill for anything but connections to main memory and perhaps high speed peripheral cores). 2. No existing IP with TileLink, so we would have to add TileLink interfaces to everything (this is in reality the same issue with Wishbone) | 07:59 |
| andrzejr | in some 3rd party presentations I've seen data buses of up to 1024b, and the timing diagrams were showing linear bursts terminated with wlast and rlast. | 07:59 |
| olofk | But AXI4-Lite doesn't have the *last signals, right? That an AXI4 thing | 08:00 |
| andrzejr | ahh, good point. My mistake, this was indeed about axi4. | 08:02 |
| andrzejr | Yes, I am not impressed with the TileLink spec. Although maybe that's what is needed for cache coherence. | 08:06 |
| andrzejr | gtg | 08:06 |
| olofk | See you | 08:06 |
| --- Log closed Tue Aug 18 00:00:05 2015 | ||
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