| --- Log opened Sat Feb 21 00:00:50 2015 | ||
| stekern | doh, I spent several minutes pondering why I hit a bus error instead of tlb miss when I turn on the mmu | 02:22 |
|---|---|---|
| stekern | turned out that I didn't have the mmu enabled in or1ksim config | 02:22 |
| dalias | stekern, :) | 03:00 |
| NCommander | Evening world | 10:21 |
| Me1234 | olofk: tracepoint_exec_pc_o[31:0] is always 0. | 11:22 |
| Me1234 | olofk: I use iwbm_adr_o[31:0] to get the pc. | 11:23 |
| Me1234 | olofk: The new SPI core generates 25 MHz clock, while the old one did 50MHz with the same bootrom.S form orpsocV2 | 12:57 |
| mor1kx | [mor1kx] bandvig pushed 1 new commit to withfpu: https://github.com/openrisc/mor1kx/commit/074e9e35e4460cb05ef2678df1218cfaba031ec0 | 13:15 |
| mor1kx | mor1kx/withfpu 074e9e3 Andrey Bacherov: Remove forcing zeros in LSB of addresses because (1) the forcing leads to impossibility to init UART during initialization of NewLIB-based program; (2) we already have got align control. | 13:15 |
| Me1234 | Serious problems with spi in orpsocv3. spiflash-program.elf must not stop working because of wrong SPI clock (25MHz instead of 50MHz)(Changed SPR bits in SPI core) | 13:33 |
| mor1kx | [mor1kx] bandvig pushed 1 new commit to withfpu: https://github.com/openrisc/mor1kx/commit/e53055101dbe9a0b60e6490defbf831371483a05 | 13:34 |
| mor1kx | mor1kx/withfpu e530551 Andrey Bacherov: (1) Some clean up... | 13:34 |
| olofk | Me1234: Yeah. This sounds bad. Do you know what bits have been changed? | 13:53 |
| Me1234 | olofk: the SPR bits. They control the clock rate | 13:53 |
| olofk | aha. I see. So that's what you meant with SPR bits | 13:54 |
| olofk | Need to take a closer look at this. | 13:55 |
| mor1kx | [mor1kx] bandvig pushed 1 new commit to withfpu: https://github.com/openrisc/mor1kx/commit/4d599fba0c1cad4255b53a240c3ecfea61ab9937 | 14:30 |
| mor1kx | mor1kx/withfpu 4d599fb Andrey Bacherov: Merge branch 'master' into withfpu | 14:30 |
| Me1234 | olofk: Uploading the vcd file. | 14:30 |
| Me1234 | olofk: Upload failed. | 14:38 |
| stekern | Me1234: nothing has changed in the spi-simple core related to the SPR bits as far as I can see | 14:45 |
| Me1234 | stekern: https://drive.google.com/file/d/0B5U7b-LVTCGtcHZlWE13REtkYm8/view?usp=sharing | 14:50 |
| Me1234 | stekern: Look here. According to the datasheet divider should be 16 | 14:51 |
| stekern | there are in fact no diffs between the orpsocv2 and fusesoc/orpsoc-cores version | 14:51 |
| stekern | ...at least no functional ones | 14:52 |
| Me1234 | stekern: Then it is more strange. | 14:55 |
| Me1234 | stekern, olofk: 4'b0000: clkcnt <= 12'h0; // 2 -- original M68HC11 coding | 14:56 |
| Me1234 | from source code od simple_spi | 14:57 |
| stekern | yes | 14:57 |
| stekern | but yours is 4'b0001, no? | 14:58 |
| Me1234 | stekern: yes | 14:58 |
| stekern | so it should be divide by 4 | 14:58 |
| Me1234 | 4'b0000: clkcnt <= 12'h0; // 2 -- original M68HC11 coding | 14:58 |
| Me1234 | stekern: accidenty pasted that again | 14:58 |
| Me1234 | 4'b0000: clkcnt <= 12'h0; // 2 -- original M68HC11 coding | 14:58 |
| Me1234 | stekern: That means that it is the sam in orpsoc v2 | 14:59 |
| stekern | you keep psting the wrong line, but yeah, 4'b0001 has always been divide by 4 | 15:00 |
| stekern | this is the first ever version released of that core: https://github.com/freecores/simple_spi/blob/67fbee0fc10d366a7ff1a72e3d711547b32a3e32/rtl/verilog/simple_spi_top.v#L239 | 15:01 |
| Me1234 | stekern: I measured the wrong interval. | 15:02 |
| Me1234 | stekern: It is 4. | 15:02 |
| Me1234 | stekern: Running on de0_nano, it goes to 0x700, which is illegal instruction exception. I think I know the cause. I forgot to increase wb_ram size form 64 to 256 | 15:05 |
| Me1234 | stekern: But it faild earlier when I ran bootrom.S with wb_ram size 256 | 15:05 |
| Me1234 | stekern: But that time I had othe orpsoc.cof | 15:07 |
| Me1234 | stekern: Will try again | 15:07 |
| Me1234 | stekern: after wb_intercon modification I need to remove wb_s2m_dbus_* decalrations from wb_intercon.conf. | 15:10 |
| Me1234 | stekern: Redeclaration errors | 15:10 |
| Me1234 | Synthezing | 15:10 |
| poke53281 | http://pastie.org/9969101 | 15:14 |
| poke53281 | Can someone see the big error? :) | 15:14 |
| poke53281 | There is only one, which matters. | 15:16 |
| stekern | poke53281: r0 isn't 0 | 15:41 |
| poke53281 | stekern: correct | 15:50 |
| poke53281 | But I don't have a clue why. | 15:51 |
| mor1kx | [mor1kx] bandvig pushed 1 new commit to withfpu: https://github.com/openrisc/mor1kx/commit/263e0ce1fa41a8c933a0a576e60a0e895bf62099 | 16:37 |
| mor1kx | mor1kx/withfpu 263e0ce Andrey Bacherov: Some Multiplexors are re-written with minor improvement in term of LUT usage | 16:37 |
| ysangkok | poke53281: did you see https://github.com/jvilk/BrowserFS ? | 18:14 |
| poke53281 | ysangkok: Yes, I starred it a long time ago. | 19:14 |
| poke53281 | A lot of the functions are not supported like rm. | 19:16 |
| poke53281 | And I am sure, that he didn't offer a full posix compatbility. | 19:19 |
| poke53281 | This were only some of the reasons, why I didn't choose to implement such a library in the beginning. | 19:20 |
| ysangkok | ok , good. im glad you considered it :) | 19:53 |
| olofk | Saw that someone on the OpenCores forum was as confused as I about the VGA timings :) | 23:04 |
| olofk | And fun to see someone with seemingly valid ideas about ISA improvements | 23:12 |
| --- Log closed Sun Feb 22 00:00:51 2015 | ||
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