| --- Log opened Mon Feb 02 00:00:23 2015 | ||
| mor1kx | [mor1kx] olofk opened pull request #23: Move localparam definition out from generate loops (master...master) https://github.com/openrisc/mor1kx/pull/23 | 07:01 |
|---|---|---|
| olofk | rschmidlin_: ^ is the patch I was talking about | 07:02 |
| olofk | knz: If I use mmap, do I need to have a reserved area of the same size in RAM? | 07:22 |
| rschmidlin_ | Very nice Olofk, tks | 07:50 |
| rschmidlin_ | I will only test this evening though | 07:51 |
| olofk | rschmidlin_: Let me know how it goes. I have some clues for your other issues as well | 07:52 |
| olofk | $clog2 is a verilog 2005 keyword, so you will need to have that enabled | 07:54 |
| olofk | The problem with ISE is that it was unsupported before ISE 13.something, and then they had a buggy implementation that didn't work at all for a few releases before the fixed it | 07:55 |
| olofk | stekern did a workaround by defining `clog2 in verilog_utils.vh that uses either the real $clog2 or a custom implementation depending on a `define | 07:56 |
| olofk | arbiter.v uses $clog2 directly, so you need a recent ISE version for that | 07:56 |
| olofk | 14.something should work | 07:56 |
| olofk | wallento: You around? | 08:12 |
| olofk | Looking for examples on how to use the irq stuff in libgloss | 08:25 |
| wallento | fo shizzle | 08:36 |
| wallento | http://openrisc.github.io/newlib/docs/html/group__or1k__interrupts.html | 08:37 |
| wallento | you need typedef void(* or1k_interrupt_handler_fptr)(void *data) | 08:37 |
| wallento | a function to be called | 08:37 |
| wallento | then: or1k_interrupt_handler_add(IRQ_LINE, &your_function, 0) | 08:38 |
| olofk | I have a small bare-metal program that stekern gave me a while ago, but it looks like that uses custom-made IRQ stuff so I'm about to port it to using proper newlib | 08:38 |
| wallento | and or1k_interrupts_enable() | 08:38 |
| wallento | sounds reasonable | 08:38 |
| olofk | Any particular order I should use? | 08:38 |
| olofk | I saw the docs already | 08:39 |
| wallento | I would not enable before adding | 08:39 |
| wallento | I see, an example is missing | 08:39 |
| wallento | if you enable before adding and the interrupt occurs, you end in exit | 08:39 |
| olofk | interrupt_enable(line) before interrupts_enable()? | 08:39 |
| wallento | no, its implicitly activated | 08:40 |
| olofk | So only interrupt_enable(line) then? | 08:40 |
| wallento | only interrupts_enable() | 08:40 |
| wallento | the enable is only necessary if you called disable before | 08:40 |
| wallento | let me shortly validate this.. | 08:41 |
| olofk | ah ok, so or1k_...add(line, callback, data) and then interrupts_enable? | 08:41 |
| wallento | correction: it is not set implicitly, but by default | 08:41 |
| wallento | I am not sure thats in the spec, so to be bullet proof, activate the line | 08:42 |
| olofk | I'll keep on doing that between the add and interrupts_enable then | 08:42 |
| wallento | I will clarify this in the documents, already started, but ran out of time :( | 08:42 |
| wallento | yes | 08:42 |
| olofk | Ran out of time? Never heard of such a thing :) | 08:42 |
| wallento | and it overlays with my sourceware frustration.. | 08:43 |
| wallento | they still experience significant issues with their servers | 08:43 |
| olofk | What the fuck is wrong with my UART now? | 08:43 |
| wallento | whats doing on? weird symbols? -> adjust baud rate | 08:44 |
| olofk | It prints out parts of the strings I'm printf'ing. Looks like it's reusing the same buffer or something | 08:45 |
| olofk | hmm.. seems like it stops after writing 16 chars | 08:46 |
| wallento | mmh | 08:46 |
| olofk | Works fine in Linux | 08:46 |
| wallento | okay, let me check | 08:47 |
| olofk | Should probably confirm this first :) | 08:47 |
| wallento | honestly my test program is "Hello World!" | 08:47 |
| wallento | < 16 characters | 08:47 |
| olofk | :) | 08:47 |
| wallento | I am sure its a bug in the UART, this is what I had to rewrite and just assumed some stuff :) | 08:48 |
| wallento | about the UART registers | 08:48 |
| wallento | I will check in the afternoon | 08:48 |
| wallento | pretty sure its something like not waiting for the FIFO to drain | 08:48 |
| olofk | I'll keep below 16 chars until then :) | 08:48 |
| olofk | That should be enough for anybody | 08:48 |
| wallento | you should wait a million clock cycles after every 16 char | 08:48 |
| olofk | I could actually try that | 08:49 |
| olofk | Does sleep work? | 08:49 |
| wallento | nope | 08:49 |
| wallento | there is no sleep | 08:49 |
| wallento | you can set a timer | 08:49 |
| olofk | for(0 to bug number); ? | 08:49 |
| wallento | this is what I usually do | 08:49 |
| olofk | Never played with the timers before | 08:50 |
| wallento | they are really confusing | 08:50 |
| wallento | there is the timer and a tick functionality | 08:50 |
| wallento | the tick is kind of a wrapper around the timer | 08:50 |
| olofk | I think my for loop is starting to sound like the best option | 08:51 |
| olofk | ...or debugging the UART driver | 08:51 |
| olofk | Just that I'm supposed to deliver the final application today :) | 08:51 |
| wallento | got it | 08:51 |
| wallento | You could have a look at the GPL code and fix it easily | 08:51 |
| wallento | but don't tell anybody ;) | 08:52 |
| olofk | I wouldn't dare. The cops will kick in the door as soon as I open a text editor with the GPL code and an empty c file | 08:53 |
| olofk | I have children now. Can't risk this | 08:53 |
| wallento | :-D | 09:04 |
| olofk | We might need a new default location for the OpenRISC linux kernel. github/openrisc/linux ? | 09:06 |
| olofk | Extremely bad timing for openrisc.net to disappear when I'm writing docs that references the kernel from there | 09:07 |
| olofk | hmm.. www.openrisc.net looks like it's back up now | 09:07 |
| knz | #openrisc: < olofk> knz: If I use mmap, do I need to have a reserved area of the same size in RAM? | 13:13 |
| knz | no | 13:13 |
| olofk | knz: I'm starting to understand how it fits together now. Alessandro's Linux Device Drivers seems to be the source of information that everybody is pointing to :) | 13:21 |
| olofk | wallento: or1k-uart.c line 67. Perhaps this should be "while (~REG8(LSR) & LSR_TFE) {}" or "while (!(REG8(LSR) & LSR_TFE)) {}" ? | 13:56 |
| wallento | yes, that makes sense | 13:59 |
| olofk | I tried the first option, and it works a little better now, but it's not working completely | 14:00 |
| wallento | okay, I am not sure this is the only required check | 14:01 |
| wallento | what is in the kernel sources? | 14:01 |
| wallento | or is it GPL :-p | 14:02 |
| olofk | I would suspect so | 14:02 |
| olofk | I'm working with the spec now | 14:02 |
| olofk | Maybe there's a bsd driver somewhere :) | 14:02 |
| olofk | ok, I reached the end of the spec now without getting any wiser | 14:04 |
| wallento | ah, I remember coding it. I was really curious why I can check for empty but not for full | 14:04 |
| wallento | yep, I also find it confusing | 14:05 |
| wallento | this is bsd: http://compbio.cs.toronto.edu/repos/snowflock/xen-3.0.3/xen/drivers/char/ns16550.c | 14:05 |
| wallento | :( | 14:05 |
| wallento | :) | 14:05 |
| olofk | Exactly! Who gives a fuck if it is empty? | 14:05 |
| wallento | this kind of clashes with my definition of a fifo | 14:08 |
| wallento | if the only check for full is that it is not empry | 14:08 |
| wallento | but, the code looks similar to ours | 14:08 |
| wallento | what are you experiencing with correct brackets? | 14:08 |
| olofk | Yes, very simimlar | 14:08 |
| olofk | Haven't tested correct brackets yet | 14:08 |
| wallento | ah, maybe try this, looks like a stupid typo.. | 14:09 |
| olofk | this == correct brackets, or something you are currently typing? :) | 14:09 |
| olofk | Nope. Doesn't fix it completely | 14:13 |
| olofk | Do I need to call uart_init explicitly btw? | 14:13 |
| olofk | Or does newlib do that? | 14:13 |
| olofk | or wait.. perhaps it does work | 14:15 |
| olofk | Yeah, I think it works now | 14:18 |
| olofk | That's a great selling point. The NEW and IMPROVED uart now supports more than 14!! different characters to suit today's demand on big data and high availability | 14:27 |
| Me1234 | I am trying to use de0_nano with ksz8051mll eval board (https://drive.google.com/file/d/0B5U7b-LVTCGtamkzMnBxRDFGQ3M/view?usp=sharing). | 14:31 |
| Me1234 | It uses mii interface. | 14:31 |
| Me1234 | I edited the quartus project generated by fusesoc to this https://drive.google.com/file/d/0B5U7b-LVTCGtN05nVGRoR0JJZDA/view?usp=sharing (details in Details.txt) | 14:31 |
| Me1234 | Linux does not boot: https://drive.google.com/file/d/0B5U7b-LVTCGtMm1qWVBBTlhrMGs/view?usp=sharing | 14:31 |
| Me1234 | I did not connect rst to the PHY because it is not in the connector. | 14:31 |
| olofk | Me1234: I just delivered a FuseSoC-based system for an Altera FPGA with Ethernet :) | 14:32 |
| olofk | ...with a Micrel Ethernet phy | 14:33 |
| Me1234 | olofk: I took parts of wb_intercon.conf and top file from neek board port | 14:35 |
| _franck___ | setup_memory: Memory: 0x0-0x2000000e size : -1066696616 bytes | 14:41 |
| _franck___ | and did you see the rest of the CPU description ? | 14:41 |
| _franck___ | there must be something wrong somewhere :) | 14:41 |
| _franck___ | bogomips : 3223330852.96 | 14:41 |
| _franck___ | Me1234: ^ | 14:47 |
| olofk | Can I read pending interrupts with OpenOCD? | 14:50 |
| _franck___ | as you can read registers, I guess you can read pending ITs | 14:52 |
| olofk | How? Are they in a SPR somewhere? | 14:53 |
| olofk | reg sr ? | 14:54 |
| Me1234 | _franck___: Linux without ethernet support also does not boot on my modified orpsoc | 14:55 |
| Me1234 | _franck___: It does not even output anyting to serial | 14:55 |
| _franck___ | olofk: I didn't say I know which register to look at ;) | 14:55 |
| Me1234 | _franck___: This linux version works on standard orpsoc | 14:55 |
| olofk | _franck_: I should be able to figure it out :) | 14:56 |
| olofk | Oh well. That's it for today | 14:56 |
| _franck___ | Me1234: you should do a diff between modified/unmodiffied and paste it (does not paste wb_intercon auto generated files) | 14:56 |
| -!- _franck___ is now known as _franck__ | 15:00 | |
| Me1234 | _franck__: diff for wb_intercon.conf: https://drive.google.com/file/d/0B5U7b-LVTCGtaGhjWVN3aG9SclE/view?usp=sharing | 15:05 |
| _franck__ | what about your top ? | 15:08 |
| wallento | olofk: lol | 15:08 |
| wallento | nice it works now | 15:08 |
| wallento | will you PR? | 15:08 |
| Me1234 | _franck__: diff for orpsoc_top.v: https://drive.google.com/file/d/0B5U7b-LVTCGtVllHMjBrd1hCcnM/view?usp=sharing | 15:09 |
| _franck__ | it looks correct. Is it all you changed ? | 15:12 |
| Me1234 | _franck__: Yes. | 15:12 |
| Me1234 | _franck__: I think the problem is in the assignments | 15:12 |
| _franck__ | are your timing requirement met ? What is your Fmax ? | 15:12 |
| _franck__ | did you add your pin assignment in the tcl file ? | 15:15 |
| Me1234 | Slow 1200 mv 0C model | 15:16 |
| Me1234 | 58.23 MHz 58.23 MHz altera_reserved_tck | 15:17 |
| Me1234 | 68.87 MHz 68.87 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[1] | 15:17 |
| Me1234 | 125.42 MHz 125.42 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[0] | 15:17 |
| Me1234 | _frank__: Slow 1200 mv 85C model | 15:17 |
| Me1234 | 112.28 MHz 112.28 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[0] 1 | 15:17 |
| Me1234 | 62.21 MHz 62.21 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[1] 2 | 15:17 |
| Me1234 | 51.53 MHz 51.53 MHz altera_reserved_tck 3 | 15:17 |
| Me1234 | _franck__: I do not know how to use timequest | 15:18 |
| Me1234 | _franck__: I pasted lines from fmax reports | 15:18 |
| _franck__ | just find Fmax and see if it is greater than your clock frequency | 15:19 |
| Me1234 | _franck__: Is it here (screenshot): https://drive.google.com/file/d/0B5U7b-LVTCGtYUdodWg2SUNnMk0/view?usp=sharing | 15:22 |
| Me1234 | _franck__: I edited the assignments in Pin planner, not in tcl. But it is no use of them: Custom connections | 15:24 |
| _franck__ | it says you can run your clk[1] (output from the pll) up to 62MHz | 15:27 |
| _franck__ | I would restart from a working design and do small steps | 15:27 |
| Me1234 | _franck__: 'working design' - You mean withount ethernet? | 15:31 |
| _franck__ | yes | 15:31 |
| Me1234 | _franck__: Connections I made https://drive.google.com/file/d/0B5U7b-LVTCGteW9SYVdYN2N2MmM/view?usp=sharing | 15:32 |
| Me1234 | _franck__: I will try to remove master interface from eth to ram and see if linux without eth boots. | 15:35 |
| Me1234 | _franck__: If it boots, It is a problem with DMA | 15:35 |
| Me1234 | _franck__: Resynthezing design | 15:35 |
| Me1234 | _franck__: Warning (332060): Node: eth0_rx_clk_pad_i was determined to be a clock but was found without an associated clock assignment. | 15:38 |
| Me1234 | _franck__: Warning (332060): Node: eth0_tx_clk_pad_i was determined to be a clock but was found without an associated clock assignment. | 15:39 |
| _franck__ | https://github.com/openrisc/orpsoc-cores/blob/master/systems/neek/data/neek.sdc | 15:39 |
| _franck__ | you need to create clocks constraint for mii clocks | 15:39 |
| _franck__ | ...however, it's not critical don't worry about this for now | 15:43 |
| Me1234 | _franck__: | 15:48 |
| Me1234 | 43.77 MHz 43.77 MHz altera_reserved_tck | 15:49 |
| Me1234 | 61.28 MHz 61.28 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[1] | 15:49 |
| Me1234 | 98.24 MHz 98.24 MHz eth0_tx_clk_pad_i | 15:49 |
| Me1234 | 107.82 MHz 107.82 MHz eth0_rx_clk_pad_i | 15:49 |
| Me1234 | 125.8 MHz 125.8 MHz clkgen0|pll0|altpll_component|auto_generated|pll1|clk[0] | 15:49 |
| _franck__ | good | 15:51 |
| Me1234 | _franck__: After I disconnected eth0 master from ram slave, the program counter does not move from 0x00000700 | 15:53 |
| Me1234_ | _franck__: Now the program conunter stays on 0xf0000104.' | 16:00 |
| Me1234_ | _franck__: Fount the problem. | 16:00 |
| Me1234_ | _franck__: Two port ram connected to three master ports (ibus disconnected) (At least now) | 16:01 |
| Me1234_ | _franck__: fixed the problem with number of ram ports, again stays at 0x00000700 | 16:13 |
| Me1234_ | _franck__: After 6 minutes it is 0x00000704 | 16:19 |
| Me1234_ | Timing problems ? | 16:20 |
| Me1234_ | _franck__: After 2 more minutes it is 0x00000708 | 16:21 |
| Me1234_ | Jumps between 0x00000708 and 0x00000700 | 16:22 |
| _franck__ | 0x700 is the handler for illegal instructions | 16:24 |
| _franck__ | that means your PC jumped somewhere | 16:25 |
| _franck__ | ... | 16:25 |
| olofk | Me1234_: Are you able to boot Linux now, but it hangs after a while? | 17:30 |
| olofk | Or doesn't it boot at all? | 17:30 |
| Ben_____ | Building the latest version of the simulator, is it normal to have 17 test fail when I run "make check"? | 18:30 |
| Me1234__ | Me1234_: It does not boot at all; I have messed something in orpsoc while trying to add ethernet. I will try to fix something tomorrow. | 19:16 |
| Me1234__ | olofk: I had many attempts; on some after orposc_top (de0_nano I tried to addd ethernet) modification linux showed ram size lower than zero, bogomips around 3200 GHZ and stopped booting. After i tried to remove master interface from eth to ram it did not boot at all. | 19:19 |
| olofk | Ben_____: See if it helps to configure with --disable-shared | 19:20 |
| olofk | There are at least some testcase that fails when or1ksim is built as a shared library | 19:21 |
| olofk | Me1234: So what you have now is original de0_nano + added ethmac core with only slave interface connected, and that doesn't boot | 19:24 |
| Me1234 | olofk: I have de0_nano with ksz8051mll external PHY. I tried with slave and master, then linux kernel showed ram size below zero, bogomips around 3200 GHZ and stopped booting. When I removed the master indterface it did not boot at all program counter moves between 0x00000700 and 0x00000708 and nothing happened. | 19:28 |
| Me1234 | With master connected diff to standard files: https://drive.google.com/file/d/0B5U7b-LVTCGtVllHMjBrd1hCcnM/view?usp=sharing and https://drive.google.com/file/d/0B5U7b-LVTCGtaGhjWVN3aG9SclE/view?usp=sharing | 19:29 |
| olofk | That all looks good, and I couldn't find anything obvious in the report files from the quartus project you sent earlier today | 19:45 |
| olofk | But I agree with _franck_ that it could be a good idea to just connect the slave interface to begin with, and try booting to get a clue about what the fuck is going on | 19:46 |
| olofk | And with the original kernel | 19:46 |
| Me1234 | olofk: I tried it. When I removed the master indterface it did not boot at all program counter moves between 0x00000700 and 0x00000708 and nothing happened. | 20:04 |
| olofk | Did you update the wb_intercon files and restore the connections to wb_sdram_ctrl? | 20:06 |
| olofk | blueCmd_, stekern, poke53282 and other ABI gurues. Can I use the Temporary registers (r13, r15, r17...) freely in a function without having to save them? | 20:10 |
| olofk | ...in the kernel | 20:15 |
| olofk | ...in a function that shouldn't call other functions | 20:16 |
| -!- antgreen` is now known as antgreen | 20:16 | |
| Me1234 | olofk: I only disconnected master interface of eth0 from sdram controller and set .WB_PORTS to 2 | 20:17 |
| olofk | Me1234: Yes, that _should_ be enough, but there is clearly something strange going on, so you could try to regenerate the wb_intercon files too just in case | 21:07 |
| olofk | basically something like this http://pastie.org/9881822 (diff from original de0_nano) | 21:10 |
| blueCmd_ | olofk: yes, temporary registers are callee-saved | 23:16 |
| --- Log closed Tue Feb 03 00:00:24 2015 | ||
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