--- Log opened Thu Dec 04 00:00:56 2014 | ||
stekern | hmm, did github fix the issues related to force-pushing to a pull-requested branch? | 06:44 |
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poke53281 | What do you mean. I had such problems. And in the end I had to push with the force option. | 06:50 |
poke53281 | But I am someone who has still no a clue about the internal functionality of git. | 06:51 |
poke53281 | A functionality which you shouldn't have to know. But here git fails a little bit. | 06:53 |
stekern | this has nothing to do with git, it's just github | 07:24 |
stekern | at least in the past, if you have a pull request open, receive comments on it, fix the issues and then force push the fixed changes, all previous discussion disappeared | 07:25 |
stekern | olofk: at least you don't have to work with this insane bus interface I'm faced with... the semantics of a read transition is: 'read the value, then assert read-enable' | 07:28 |
olofk | stekern: Like a I-can-now-confirm-that-I-have-read-the-value signal? | 08:12 |
stekern | yes | 08:22 |
stekern | but it's just called 'read', to ensure that you get confused how to expect that it'd work | 08:23 |
stekern | maybe they intended it to be read as 'redd' not 'reed' ;) | 08:25 |
olofk | The dual tempus of read is a very annoying bug | 08:40 |
olofk | The number of corner cases in my upsizer is incredible. I would have been completely lost without the new BFM | 08:41 |
olofk | Well, I'm still pretty lost with it | 09:04 |
olofk | Yeah! Passed 5000 transactions now | 09:27 |
olofk | 50000 transactions! | 09:30 |
olofk | Just a little worried since I'm testing against my own implementation | 09:31 |
olofk | Oh well. Time to write the (world's?) first 64-bit wishbone core | 09:31 |
stekern | olofk: master of VHDL, tell me, is there a clog2 (or similar) function? | 09:52 |
stekern | or do I have to roll my own? | 09:52 |
olofk | Nope. You need to roll your own | 09:53 |
olofk | But at least you can put it in a package so that it can be used in the header as well | 09:53 |
stekern | yeah, I just wanted to avoid re-inventing the wheel if not necessary | 09:54 |
stekern | so much time goes to pondering about what types signals should have and converting between them... | 10:12 |
stekern | my_sig(to_integer(unsigned(addr))); is my favourite | 10:13 |
olofk | stekern: Yep. Love that as well. There is a poll on the VHDL mailing list about what propsed features that people would actually use. Closes today | 12:35 |
olofk | I think that nicer conversion from std_logic_vector <-> integer is on the list | 12:36 |
-!- Netsplit *.net <-> *.split quits: trem | 17:13 | |
--- Log closed Fri Dec 05 00:00:57 2014 |
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