| stekern | that's good, I guess ;) | 00:28 |
|---|---|---|
| stekern | ok, here goes nothing | 01:21 |
| mor1kx | [mor1kx] skristiansson pushed 9 new commits to master: https://github.com/openrisc/mor1kx/compare/e11294b50bd8...70115880e791 | 01:22 |
| mor1kx | mor1kx/master e4a3f8c Stefan Kristiansson: cappuccino/fetch: use exception branch signal to deassert fetch exceptions... | 01:22 |
| mor1kx | mor1kx/master e0096b3 Stefan Kristiansson: cappuccino: prepare fetch and icache for immu... | 01:22 |
| mor1kx | mor1kx/master 023b35d Stefan Kristiansson: cappuccino/ctrl: remove execute_valid_i from except_range | 01:22 |
| stekern | everything is in there now | 01:23 |
| juliusb | FEATURE_ADDC costs 25 LUTs on Xilinx Spartan 6 | 02:18 |
| juliusb | stekern: nicely done mate :) You've earned a beer :) | 02:19 |
| juliusb | so does that mean now mor1kx is a lean mean Linux running machine? | 02:19 |
| glowplug | No way you guys can boot the kernel on mor1kx? | 02:20 |
| juliusb | way, I believe. | 02:20 |
| glowplug | That is amazing! | 02:21 |
| juliusb | no, i'm wrong on that | 02:44 |
| juliusb | sorry, not the Linux thing | 02:44 |
| juliusb | the ADDC cost | 02:44 |
| juliusb | the cost is -25LUTs | 02:44 |
| juliusb | I assumed the smaller was without ADDC | 02:44 |
| juliusb | but it's _with_ ADDC that it's 25 LUTs less than without! | 02:45 |
| glowplug | Only Xilinx probably knows why... | 02:45 |
| juliusb | well, i think something's getting optimised better | 02:46 |
| juliusb | FEATURE_RANGE costs 4 FF and 27 LUT on Spartan 6 | 02:49 |
| juliusb | so nothing better if you have that in there :) | 02:49 |
| glowplug | Heres an interesting fact. If you google "verilog feature_range" the only results are the mor1kx git repo. O_O | 02:50 |
| glowplug | Guess I won't be learning what THAT does today. :/ | 02:51 |
| juliusb | so espresso vs prontoespresso, FF: 914 vs 807, and LUT: 2504 vs 2454 | 02:53 |
| juliusb | so saving of 90 FF and 50 LUT for pronto (also no delay slot.. the best!) | 02:53 |
| glowplug | Wow I didn't know that the core itself was already down to ~2500 LUT usage. Thats really really insanely good. | 02:54 |
| juliusb | really?! | 02:55 |
| glowplug | How do peripherals use ~8k? The code must be muck! | 02:55 |
| juliusb | this is spartan 6 with debug, UART and RAM, in tital os 2k FF and 4.4K LUT | 02:55 |
| juliusb | so CPU is about half of this system but it's a minimal one | 02:56 |
| glowplug | I've been trying to design an FPGA board with ~15k LE's for development. What peripherals use so many elements? | 02:56 |
| juliusb | ethernet | 02:56 |
| juliusb | an ethernet MAC (soft) will chew your LEs | 02:56 |
| glowplug | Thats nonsense. You can get a TTL ethernet adaptor for $3. Theres no need for the IP ethernet. | 02:57 |
| juliusb | what's the interface to it? | 02:57 |
| glowplug | TTL. | 02:58 |
| juliusb | sure above that I mean | 02:58 |
| juliusb | what goes over the TTL connection? | 02:58 |
| juliusb | you're talking about a small network processor? | 02:58 |
| glowplug | Let me find a link. | 02:58 |
| glowplug | http://bit.ly/14Xww5o | 02:59 |
| glowplug | Wups I'm sorry. It's SPI not TTL. I'm thinking of a different module. | 03:00 |
| glowplug | There are kernel drivers for the module however. | 03:02 |
| juliusb | so if both FEATURE_ADDC and FEATURE_RANGE are off, then you save 63 LUT it seems | 03:02 |
| juliusb | takes you to 2391 LUT | 03:02 |
| glowplug | It looks like there is a driver on the opencores site for ENC28J60 actually. | 03:04 |
| glowplug | http://opencores.org/websvn,filedetails?repname=igor&path=%2Figor%2Ftrunk%2Favr%2Fsrc%2Fdev%2Fenc28j60.h | 03:04 |
| glowplug | Is that enough to use the ENC28J60 with your FPGA board? | 03:04 |
| juliusb | jeese the serial divider costs you a bit in mor1kx - 104 FF and 266 LUT | 03:07 |
| juliusb | oh wow fair neough | 03:07 |
| juliusb | (ethernet) | 03:07 |
| juliusb | that ethernet guy is probably not very fast | 03:08 |
| glowplug | No. But neither is the CPU! Haha | 03:08 |
| juliusb | and you need a CPU to sit there and micromanage it on receive | 03:08 |
| juliusb | well, on everything actually | 03:08 |
| glowplug | Obviously we have Xilinx to blame for that. | 03:08 |
| juliusb | the benefit of having an on-FPGA ethernet MAC is that you can give it DMA | 03:09 |
| juliusb | well Xilinx would probably tell you to use their hard ethernet MAC block | 03:09 |
| glowplug | With the drawback of increasing devboard cost by 8 times. Haha | 03:09 |
| juliusb | but that's not entirely portable between FPGA families I guess | 03:09 |
| juliusb | interesting - barrel shifter (versus serial shifter) costs -31FF and 209 LUT | 03:11 |
| juliusb | that makes sense | 03:11 |
| glowplug | I will order one because it will probably arrive after I have working prototypes of the FPGA board. My guess is that network traffic at that level won't cause a huge problem. | 03:12 |
| juliusb | OK that's enough synthesis play for tonight | 03:12 |
| glowplug | So you actually had a functional linux boot on the Xilinx device? | 03:13 |
| juliusb | sure... the OR1200 runs Linux | 03:17 |
| juliusb | the mor1kx does now too, thanks to stekern's work | 03:17 |
| juliusb | really going now - good night | 03:17 |
| glowplug | I know that OR1200 does. I'm mostly interested in mor1kx. =) | 03:17 |
| glowplug | Night and congradulations on your progress! | 03:18 |
| stekern | glowplug: I've only been testing on my de0-nano (cyclone iv) so far, but should work on spartan 6 as well | 07:09 |
| stekern | that's my next step testing on the atlys board | 07:09 |
| stekern | spartan slices and altera le's aren't comparable btw | 07:12 |
| stekern | I think I have bloated the cappuccino lately though... | 07:13 |
| stekern | so plan now, dcache rework, then optimizing | 07:14 |
| mor1kx | [mor1kx] skristiansson pushed 1 new commit to master: https://github.com/openrisc/mor1kx/commit/fd14d9e82e6092e964fc46fcf52e02c6d724a136 | 10:15 |
| mor1kx | mor1kx/master fd14d9e Stefan Kristiansson: cappuccino: propagate IMMU/DMMU parameters into cfgrs | 10:15 |
| stekern | hmm, there's not even uart printout on the atlys now... | 10:17 |
| stekern | I can't believe it'd be that broken, have to be something external I've screwed up | 10:17 |
| stekern | last I tested on the atlys board, I ran at 80 MHz, so maybe some leftovers from that I haven't restored | 10:18 |
| stekern | looks like it really is that broken :( | 12:27 |
| stekern | going back to earlier commits works | 12:27 |
| stekern | git bisect, here I come! | 12:28 |
| juliusb | good luck stekern ! I'm out today | 12:33 |
| stekern | what a surpise, it bisects into the commit that does most of the fetch rewrite... | 15:16 |
| stekern | juliusb: I need to get some simulations going, what do you reckon is easiest, set things up in mor1kx-devenv or move stuff over to orpsoc? | 18:07 |
| stekern | nm, it was just a matter of adding three lines of code and copying one file | 20:21 |
| GentlemanEnginee | Hello. | 20:50 |
| glowplug | How's it going? | 20:54 |
| GentlemanEnginee | I thought you might be here... | 20:54 |
| glowplug | Haha | 20:55 |
| GentlemanEnginee | I have started looking at the MilkyMist Memory Controller. | 20:56 |
| GentlemanEnginee | It will take some time. | 20:56 |
| GentlemanEnginee | Any progress on your Xilinx Board? | 20:56 |
| glowplug | Negative. I'm contemplating a cheaper 2 layer design because apparently the mor1kx cpu uses far less LE's than I previously thought. | 20:59 |
| glowplug | There is one example of a 2 layer board. Its called the Papilio. And it has an absolute shit license (creative commons asshole license). | 21:00 |
| GentlemanEnginee | I thought you had ascertained that the soc used ~12 LEs. | 21:00 |
| GentlemanEnginee | I haven't heard of that variation of CC... | 21:00 |
| glowplug | Apparently just the CPU uses only 2k. | 21:01 |
| glowplug | And most of those peripherals can be replaced by a dirt cheap uC. | 21:01 |
| GentlemanEnginee | Of course. | 21:01 |
| glowplug | Yeah. The license means that the design cannot be used for commercial licenses. So its useless. | 21:01 |
| glowplug | *commercial purposes | 21:02 |
| GentlemanEnginee | However, if one starts replacing peripherals with a uC, why not just use a uC for the entirety? | 21:02 |
| glowplug | Because the peripherals don't need development. =) | 21:02 |
| glowplug | The idea is to make the cheapest possible devboard for openrisc development. I think that can be done on a 2 layer PCB for less than $25 total. | 21:02 |
| GentlemanEnginee | If you are wishing to expand the performance of the uC Core, it would serve purpose. However, one would not be able to do much more. | 21:03 |
| glowplug | Ultimately yes we should try to avoid any proprietary technology. But until we can make our own ASICs (which might not be far off). We need to reply on proprietary FPGA's anyways. At least we can use them for development until we take over. Sounds evil when you put it that way... | 21:04 |
| GentlemanEnginee | I imagine that additional work will be required for the peripherals, if one wishes to optimize them for an ASIC at some point. | 21:04 |
| glowplug | The amount of "work" needed on the CPU core is technically infinite. So I would say such a devboard would remain relevant for a long time. =) | 21:05 |
| glowplug | *rely not reply | 21:05 |
| GentlemanEnginee | What was the response for the other organization in terms of a limited run? | 21:05 |
| glowplug | No email yet. Which tells me they dont really care. | 21:06 |
| glowplug | And thats fine because 2-layer is better for this. | 21:06 |
| glowplug | It means that will some patience *anyone* could build this board at home. | 21:06 |
| glowplug | No fab shop required. | 21:06 |
| GentlemanEnginee | I *do* like a two-layer board. However, would it be able to cope with a decent sized FPGA? | 21:07 |
| glowplug | Nope. It will probably be only 5k or 10k LE's. | 21:07 |
| glowplug | But if it can get an openrisc system booted into the linux kernel then thats all we really need. | 21:08 |
| GentlemanEnginee | That means that to develop the SoC will likely require another board. | 21:08 |
| glowplug | Oh no! | 21:08 |
| GentlemanEnginee | Sarcasm? | 21:08 |
| glowplug | No haha | 21:08 |
| glowplug | It wont require another board. =) | 21:08 |
| glowplug | All you really need is the cpu and memory controller. | 21:09 |
| glowplug | That will fit in ~3k LE's | 21:09 |
| glowplug | The other ~8k were being used by peripherals like ethernet that a uC can do for way way cheaper. | 21:09 |
| GentlemanEnginee | Yes, but would not an SoC require all of these? | 21:10 |
| glowplug | You mean if it was manufactured as an ASIC in the future? | 21:11 |
| glowplug | Sure but I dont think any work has been done to those peripherals in years. They are just stuck in there and glued together. | 21:12 |
| GentlemanEnginee | Yes. To develop the SoC will require that all of the peripherals are also tested and optimized. | 21:12 |
| glowplug | That is so very very far off though. | 21:12 |
| glowplug | The purpose of this device would be to encourage distributed development. The more working the better. | 21:12 |
| glowplug | An ASIC project is a massive million dollor + mission. Everyone involved would have massively expensive development tools. | 21:13 |
| GentlemanEnginee | It would be ideal if the development board would be able to handle such a task, though... | 21:13 |
| stekern | glowplug: but ethernet on a external uC will be slooow, like juliusb said yesterday | 21:13 |
| glowplug | Ethernet on the chip I linked is very slow. | 21:14 |
| glowplug | However. Ethernet on a pic32 is very very fast. There is a parallel interconnect bus that you use to communicate with the FPGA. | 21:14 |
| GentlemanEnginee | If the Ethernet is on the same FPGA as the core, I imagine the same manner of speed will be realized. | 21:15 |
| stekern | but then you'd need a core that speaks to that bus | 21:15 |
| glowplug | Yes. At 4x the FPGA cost. | 21:15 |
| glowplug | A linux kernel driver can communicate with the pic32. | 21:15 |
| GentlemanEnginee | We were looking at ~$40 before, correct? | 21:16 |
| glowplug | Right. And $1800 minimum board order. | 21:16 |
| glowplug | The new design would be DIY board. $25 component cost. | 21:16 |
| GentlemanEnginee | So, the $15 delta would allow for a much larger system. | 21:17 |
| glowplug | The communication between the driver and the pic32 would be exactly as fast as lets say a PCI 66mhz network card wired up to the FPGA. Same idea. | 21:17 |
| glowplug | Its not $15 more though. Its $15 more per board component cost + $1800 minimum board order. | 21:18 |
| GentlemanEnginee | If there 45 interested parties, it is only $15 more. | 21:19 |
| glowplug | Plus the risk of BGA soldering. | 21:19 |
| glowplug | Yes. In theory. Haha | 21:19 |
| GentlemanEnginee | True. | 21:19 |
| glowplug | Heres the problem though. | 21:19 |
| GentlemanEnginee | What? | 21:19 |
| glowplug | I or someone would have to order the $1800 in boards up front. | 21:19 |
| glowplug | To prove that it even works. | 21:20 |
| glowplug | Then you could distribute to the ~45 people. | 21:20 |
| GentlemanEnginee | I thought it was a tried and true desing. | 21:20 |
| GentlemanEnginee | *design. | 21:20 |
| stekern | heh, this simulation doesn't work at all... not even with or1200 | 21:20 |
| glowplug | And if someone fails the BGA soldering. They are out a board and FPGA. | 21:20 |
| glowplug | It is tried. I'm not sure about true. | 21:20 |
| GentlemanEnginee | I assume it works well enough to be used... | 21:21 |
| glowplug | You are right the economics slightly favor the bigger board. But a lot of elements have to fall into place. | 21:21 |
| glowplug | The 2-layer DIY board would run the cpu perfectly and even boot linux. It would have 512mb of DDR, ethernet, usb, and even an on-board JTAG programmer. | 21:22 |
| GentlemanEnginee | If we could have the payment initially from interested parties, we could even have the board assembled. | 21:22 |
| glowplug | Yes that would be a convenience. Haha | 21:22 |
| glowplug | I would be a lot more comfortable with designing and manufacturing the prototypes myself. | 21:23 |
| GentlemanEnginee | If there are sufficient interested parties, it would be the direction I would suggest. | 21:23 |
| glowplug | I really like Quandary. And I will be stealing a lot of their ideas. Ahem.. using. | 21:23 |
| GentlemanEnginee | I am unfamiliar with Quandary. | 21:24 |
| glowplug | Thats the name of the Numato board. | 21:24 |
| glowplug | Actually. Here is another way to look at it. | 21:24 |
| GentlemanEnginee | What? | 21:24 |
| glowplug | Quandary is close enough in features and cost to the DE0 Nano that probably everyone should choose that platform instead. | 21:24 |
| glowplug | But a 2 layer board at only $25 is such a different price/feature point it wouldnt compete with the Nano. I think it would be more attractive. | 21:25 |
| glowplug | Also you have to consider distributed development is not just about features per dollor. It comes down to "can I even afford this toy". For a lot of students and others $25 is possible, $50 is not. | 21:26 |
| glowplug | This is why Arduino is so popular even though $50-$100 devkits existed way before Arduino. | 21:26 |
| GentlemanEnginee | I suppose... | 21:27 |
| glowplug | And there is another reason. | 21:28 |
| glowplug | I plan to make the prototype on glass. =) | 21:28 |
| GentlemanEnginee | If we design this, I might even be able to run the design past some of my collegues in order to avoid large pitfalls. | 21:29 |
| glowplug | That would be great! | 21:29 |
| GentlemanEnginee | FR4 is fiberglass. I assume you are referring to somthing more exotic. | 21:29 |
| glowplug | I am EXTREMELY new at kicad. Some review would be greatly appreciated. =) | 21:29 |
| glowplug | Glass microscope slides. 8) | 21:30 |
| GentlemanEnginee | My Kicad experience is rather limited as well. I have used pcb in the past. | 21:30 |
| glowplug | 3.6x3.1x1.2 inches | 21:30 |
| GentlemanEnginee | How would one lay out the copper? | 21:30 |
| glowplug | Glass glue the copper foil onto the slide. Roll on photo resist. Develop. Etch. | 21:31 |
| GentlemanEnginee | I suppose. | 21:32 |
| GentlemanEnginee | I have read about such. | 21:32 |
| glowplug | Not only do you get a clear PCB (very cool). The slides are $7 for 72. | 21:32 |
| glowplug | Copper foil is insanely cheap. | 21:32 |
| GentlemanEnginee | I imagine the Cu and photo-resist would add to that. | 21:32 |
| glowplug | Yes but the end result is still cheaper. I have to use photo resist for my regular boards anyways. | 21:33 |
| GentlemanEnginee | One would also need a very powerful adhesive in order to prevent the pads from raising during soldering. | 21:33 |
| glowplug | There is a youtube video one second. | 21:33 |
| glowplug | http://www.youtube.com/watch?v=Rf5HBLzDGQA | 21:34 |
| GentlemanEnginee | That is interesting. | 21:35 |
| GentlemanEnginee | I also suggest you pass the concept around to several of the more senior members of this channel. | 21:36 |
| GentlemanEnginee | That could prevent us from designing something that would be little more than a plaything for the two of us. | 21:36 |
| glowplug | Naw I'll just build it. If its a massive failure then I will just keep it to myself. If it works then I will show the world. Haha | 21:36 |
| glowplug | It really could either work or not work. In terms of features it doesn't need anything special. | 21:37 |
| GentlemanEnginee | Asking for advice on the concept could avoid wasting a large amount of time at a later date. | 21:38 |
| glowplug | http://papilio.cc/index.php?n=Papilio.Hardware | 21:38 |
| glowplug | That is the board with the horrible license. Its 2 layer though. | 21:38 |
| GentlemanEnginee | Are you stating that you wish to conduct this entire endevour solo? | 21:39 |
| glowplug | The time wont be wasted. I plan to use my design for motion control. SO if nobody else likes it thats fine. =) | 21:39 |
| glowplug | If I can get help that would be great! I will have all files on a github repo that anyone can fork. | 21:39 |
| glowplug | Going to subway back in a few. =) | 21:40 |
| GentlemanEnginee | Restaurant or means of transportation? | 21:40 |
| glowplug | Haha | 22:03 |
| glowplug | Restaurant (if you can call it that). =) | 22:04 |
| GentlemanEnginee | I was being generous... | 22:06 |
| glowplug | It IS tasty though. 8) | 22:06 |
| GentlemanEnginee | However, I have been known to dine on a Brooklyn-Manhattan Transit. | 22:06 |
| glowplug | I live in the Detroit area. No public transportation here except horrible busses. | 22:07 |
| GentlemanEnginee | Subway Restaurants serve the BMT (as above). | 22:08 |
| glowplug | Wait there are actually subways in the subway? | 22:08 |
| GentlemanEnginee | The second Subway location was in a subway station. | 22:09 |
| GentlemanEnginee | The BMT sandwich stands for Brookly-Manhattan Transit. | 22:10 |
| glowplug | I did not know that at all. That is actually awesome. | 22:10 |
| glowplug | I remember thinking to myself. What the hell ingredients stand for BMT. | 22:11 |
| glowplug | Never googled it though. | 22:11 |
| GentlemanEnginee | Order it by its full name to be greeted by blank stares... | 22:12 |
| glowplug | Especially here. O_O | 22:12 |
| GentlemanEnginee | Give the instruction "equal volume of onions as lettuce", and it will have to be repeated on average of 3.6 times. | 22:13 |
| glowplug | http://www.thedailyrage.com/wp-content/uploads/2009/03/subwaychipotle.png | 22:14 |
| GentlemanEnginee | I have never had that issue... | 22:14 |
| glowplug | So anyways. Haha | 22:15 |
| glowplug | Did you take a look at the papilio board? | 22:15 |
| GentlemanEnginee | I *do* think that if the concept of the board appeals to the broadest range of developers, it will increase its likelyhood of success. | 22:16 |
| GentlemanEnginee | In that vein, I would re-itterate my suggestion that the concept be passed by some others on this channel. | 22:18 |
| glowplug | I probably will get the gitpage linked at least. I will have a readme on there for anyone interested. | 22:19 |
| glowplug | You can see the papilio is only $38 but it has no RAM. | 22:20 |
| glowplug | I need to pack that thing into 3 inches by 1 inch. | 22:21 |
| GentlemanEnginee | You think that RAM would be possible at a $25 pricepoint? | 22:21 |
| glowplug | Sure. The RAM modules are only ~$4 in bulk. I could probably get away with 256mb actually. | 22:21 |
| GentlemanEnginee | Let us look at a schematic prior to marrying ourself to a form factor. | 22:22 |
| glowplug | I have the papilio schematic. =) | 22:22 |
| GentlemanEnginee | Yes. However, in order to avoid their license, it will have to be re-desiged. | 22:23 |
| GentlemanEnginee | *re-designed. | 22:23 |
| glowplug | It is 2.7x2.7 | 22:23 |
| GentlemanEnginee | Also, you wished to incorporate components of the other board. | 22:23 |
| glowplug | Yeah basically copied. With some minor changes. | 22:23 |
| glowplug | It wont be possible to tell because the formfactor is completely different and its kicad not eagle. | 22:23 |
| GentlemanEnginee | Board form factor. | 22:25 |
| glowplug | If I can't fit everything into 3x1 I will make it a SODIMM module. | 22:26 |
| glowplug | And put all of the peripherals on a seperate board with a SODIMM socket. | 22:27 |
| GentlemanEnginee | Which FPGA are you intending on? | 22:27 |
| glowplug | I'm blind. | 22:30 |
| glowplug | http://papilio.cc/index.php?n=Papilio.PapilioPro | 22:30 |
| glowplug | Eagle schematics on that page. The board has a spartan-6 and a RAM module. | 22:30 |
| GentlemanEnginee | I have been reading the documentation on the miklymist memory controller. | 22:31 |
| glowplug | I have the board statistics up for the papilio pro. It is infact 2 layers with a RAM module. =) | 22:32 |
| GentlemanEnginee | The documentation states that only the Virtex 4 is supported. However, their is a Sparan 6 directory with Verilog. | 22:32 |
| glowplug | Interesting. If thats true then I should probably use the Spartan-6. | 22:32 |
| glowplug | The RAM module in this design is MT48LC4M16. | 22:33 |
| GentlemanEnginee | What are the timings of that module? | 22:34 |
| glowplug | Not sure but I'll use MT48LC16M16A2P-75 anyways. | 22:35 |
| glowplug | 256MBit module. | 22:35 |
| glowplug | They are $4.50 each in volume. | 22:36 |
| GentlemanEnginee | What are the parameters on that chip? | 22:36 |
| glowplug | Its an SDRAM module which means it wont need the MilkyMist controller. | 22:37 |
| glowplug | I could try to get a DDR module onto the 2-layer design though. | 22:37 |
| glowplug | The problem with DDR is I think the traces need to be all exactly the same length. | 22:37 |
| GentlemanEnginee | It is a requirement. | 22:39 |
| glowplug | Yeah... | 22:39 |
| glowplug | http://papilio.cc/uploads/Papilio/ppro.jpg | 22:40 |
| glowplug | I could put the RAM module on a 2-layer DIMM. Bring out all the traces to contacts at exactly the same length. | 22:41 |
| glowplug | That could be done DIY. You would plug the DDR module into the mainboard. | 22:41 |
| glowplug | http://www.digikey.com/product-detail/en/1565918-4/A97499CT-ND/1619812 | 22:45 |
| glowplug | $3.50 in bulk kind of pricey. Might be able to find for less. 200 pins. | 22:46 |
| GentlemanEnginee | With the size of the FPGA, (22mm pin to pin), I do not believe your 3x1 inch board size is fairly unobtainable. | 22:46 |
| GentlemanEnginee | Sorry. I *do* believe your 3x1 inch board size is fairly unobtainable. | 22:47 |
| glowplug | It could still be done. | 22:49 |
| glowplug | The side and bottom row are fine. The top row would have a struggle. | 22:49 |
| GentlemanEnginee | Even on the sides, there are design constraints on pads or traces close to edge of board. | 22:50 |
| glowplug | Your right. TQFP is 22mm from pin to pin. Interesting. | 22:51 |
| GentlemanEnginee | I assume that is the package you were intending on using. | 22:52 |
| glowplug | It is. There is a $15 module with 9k LE's | 22:52 |
| GentlemanEnginee | There is a reason FPGA boards are rarely narrow rectangles. | 22:54 |
| glowplug | In the case of papilio that is mostly because he has a pin header for every pin. We dont need that. | 22:54 |
| GentlemanEnginee | Yes. However, the FPGA Package itself is a square. | 22:55 |
| GentlemanEnginee | You can cut your own glass. | 22:55 |
| GentlemanEnginee | Use an old window. It could be even less expensive than purchasing slides. | 22:56 |
| glowplug | I would very much like to avoid that. Haha | 22:58 |
| GentlemanEnginee | It *would* give a whole new meaning to database shard... | 22:59 |
| glowplug | Haha | 23:02 |
| GentlemanEnginee | I do think DDR would be nice, if it could be managed. | 23:02 |
| glowplug | I still think it can be done at 25x75mm. | 23:02 |
| GentlemanEnginee | Once a schematic is created, the pcb can be modeled. | 23:03 |
| glowplug | I actually don't know why the RAM module is on the top of the papilio pro. | 23:09 |
| glowplug | The backside is almost completely unused. Its actually almost a 1 layer design. O_O | 23:10 |
| GentlemanEnginee | BRB. Restarting Emacs. | 23:15 |
| GentlemanEnginee | Back | 23:17 |
| glowplug | You use erc too. Haha | 23:20 |
| glowplug | Oh man... | 23:20 |
| glowplug | http://bit.ly/SvD3Ex | 23:20 |
| glowplug | That unit is pretty sick. $52 with Cyclone IV and 256MB SDRAM. | 23:21 |
| _franck_ | glowplug: if you don't have component on the bottom side, you don't have paste mask tooling cost (if your pay for assembly) | 23:23 |
| glowplug | I see! Thank you _franck_ | 23:25 |
| glowplug | I'm sure Papilio had the boards made so that explains it. | 23:25 |
| glowplug | I don't care about that so I'll put the RAM module on the back. 8) | 23:25 |
| glowplug | That does severely complicate assembly though... hmm | 23:27 |
| glowplug | Thats a tough call. | 23:27 |
| glowplug | This design is quite good. http://img02.taobaocdn.com/imgextra/i2/325106443/T29upiXnVNXXXXXXXX_!!325106443.jpg | 23:27 |
| _franck_ | are you going to hand solder your board ? | 23:28 |
| glowplug | If I put the RAM module on the back it would either have to be hand soldered or laser. | 23:28 |
| glowplug | I might have to abandon the 25mm width design. =( | 23:29 |
| GentlemanEnginee | It is a shame. | 23:31 |
| GentlemanEnginee | How many LEs? | 23:31 |
| glowplug | 9K | 23:32 |
| glowplug | Oh you mean on the Ebay board? | 23:32 |
| glowplug | I think its 10k. | 23:32 |
| _franck_ | why do yo want to make 2 layers pcb ? I just made a quote at pcbcart for 50mmx50mm 4 layers boards, it is $4 (or $2 for 75 boards)... (but tooling cost is $100) | 23:36 |
| GentlemanEnginee | What programming is required? | 23:37 |
| _franck_ | http://picpaste.com/pics/Sans_titre-NKveB2TX.1363556306.png | 23:38 |
| glowplug | 2 Layer so the boards can be made DIY. | 23:38 |
| glowplug | Interesting. Where is the qoute from? | 23:39 |
| _franck_ | www.pcbcart.com | 23:40 |
| glowplug | So the total is 10 euro per board at 20 count. | 23:40 |
| glowplug | I get 3.30 euro per board at 75 count + tooling. | 23:41 |
| glowplug | Thats pretty affordable... | 23:41 |
| _franck_ | it is | 23:42 |
| glowplug | Certainly less fun... | 23:43 |
| _franck_ | 500 pcs = 0.80 euro each board :) | 23:43 |
| glowplug | Is the tooling cost always 100 euro? | 23:43 |
| _franck_ | yes | 23:44 |
| glowplug | Interesting that is really really cheap. | 23:44 |
| glowplug | The main drawback is that it would cost $200 every time I need to make a small adjustment. And I can't DIY 4-layer at least not easily. | 23:45 |
| glowplug | So unless I get the board design right the first or second time the costs would be very high to me. Cheap for everyone else. Haha | 23:46 |
| glowplug | At any rate thanks for the information. =) | 23:46 |
| glowplug | BRB | 23:46 |
| _franck_ | true. But it's not a complex design...it's goinf to work first time | 23:47 |
| _franck_ | s/goinf/going | 23:47 |
| GentlemanEnginee | :) | 23:47 |
| _franck_ | damned ! I just realised my "non official license" for polar si8000 expired on 01/2013 .....and there is no way to find a solution on the web for now :( | 23:50 |
| GentlemanEnginee | I detest licences. | 23:51 |
| _franck_ | I'll try to find something free | 23:53 |
| GentlemanEnginee | *channels inner Stallman* That is always best... | 23:54 |
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