| olofk | juliusb: Hey, I thought I was the coolest thing you've ever seen | 00:07 |
|---|---|---|
| olofk | ok, you said one of the coolest. Fair enough | 00:08 |
| poke53281 | Thanks juliusb | 00:19 |
| @juliusb | :) | 00:31 |
| @juliusb | man, document editing sucks | 02:52 |
| @juliusb | chews up so much time! | 02:52 |
| michael_ | hi | 05:28 |
| michael_ | juliusb | 05:28 |
| stekern | juliusb: how rude of you to not answer within 2 minutes :( | 05:33 |
| stekern | juliusb: I did a synthesis test on espresso as well, there I actually got a resource _decrease_ by ~1% and fmax increase by ~10% | 06:55 |
| @juliusb | stekern: yep, I know, i'm pretty rude :) | 11:36 |
| @juliusb | stekern: great work with those changes then | 11:36 |
| @juliusb | have I pulled them in yet? | 11:36 |
| mor1kx | [mor1kx] juliusbaxter pushed 8 new commits to master: https://github.com/openrisc/mor1kx/compare/343c31764f7c...d5231383c5c9 | 11:38 |
| mor1kx | mor1kx/master d273ffd Stefan Kristiansson: cappuccino/cpu: whitespace cleanup | 11:38 |
| mor1kx | mor1kx/master 8dcc9fb Stefan Kristiansson: espresso/lsu: whitespace cleanup | 11:38 |
| mor1kx | mor1kx/master 45f83c3 Stefan Kristiansson: lsu: rename alu_result_i to lsu_adr_i | 11:38 |
| @juliusb | ok, merged | 11:38 |
| stekern | yup, nice got another set prepared this morning ;) | 12:01 |
| stekern | I think the rest is just cappuccino changes though | 12:01 |
| stekern | a small change in decode to output a branch indication and branch target | 12:02 |
| stekern | I managed to refractor that so most of what I had there is now in ctrl_branch | 12:03 |
| stekern | I think the dsx passing with my pipeline rework branch is just a coincident, it still fails in my for-openrisc branch when I merged in the changes I thought would have fixed that | 12:04 |
| stekern | looks like it's a branch and an exception that happens at (almost) the same time and the branch target get confused somehow | 12:04 |
| stekern | so I'm going to look a bit more at that to make sure there won't be any bugs lurking around related to that | 12:05 |
| @juliusb | stekern: (DSX fail) is it a confused branch target or a confused EPCR? | 13:01 |
| @juliusb | this is the thing I noticed | 13:02 |
| @juliusb | and was trying to fix | 13:02 |
| stekern | confused branch target | 13:02 |
| stekern | the confused EPCR I have fixed | 13:03 |
| @juliusb | it's probably different now, but after the delay slot instruction had completed, and the branch had been indicated to the fetch unit, the control stage forgot it was in a delay slot, and if there's an exception, it sets the EPCR to the delay slot instruction, and should, instead, set it to the branch target | 13:03 |
| @juliusb | oh great :) | 13:03 |
| stekern | that was the failing intloop test | 13:03 |
| @juliusb | great | 13:03 |
| stekern | it's not in openrisc/mor1kx yet though, but queued up | 13:03 |
| @juliusb | cool | 13:04 |
| stekern | the DSX fail is a bit odd, it has a lsw with misalign in a delay slot to a bf, the bf should branch to test_func, but instead the test_func branch target is confused into being test_fail when the exception comes one cycle after the l.bf | 13:06 |
| @juliusb | hmmm | 13:07 |
| @juliusb | ya, odd | 13:07 |
| stekern | but I just ran the test after merging the changes I thought would fix it before 'running' off to work this morning | 13:08 |
| stekern | so haven't looked at it in detail | 13:08 |
| stekern | ok, so I think I've figured out the DSX fail and why it's not happening in my pipeline rework | 18:19 |
| stekern | the sequence is the following: l.sfeq r0,r0; l.bf test_func; l.lwz r1,1(r0); test_func: l.jr r9 | 18:21 |
| stekern | so the exception in the delay_slot (the l.lwz r1,1(r0)) will be generated one cycle after l.jr r9 is in execute | 18:23 |
| stekern | and when l.jr is in execute, it will generate ctrl_branch_occur (so before the exception) | 18:23 |
| stekern | in my pipeline rework I introduced the pipeline bubble on such conditions, to prevent the fetcher from being confused when ctrl/mem stage is stalling a jump | 18:24 |
| stekern | so there it can't happen | 18:24 |
| stekern | i.e. the condition = a jump following a load/store | 18:25 |
| olofk | Planned downtime | 20:51 |
| @juliusb | olofk: that was quick | 23:12 |
| @juliusb | stekern: very good, what about some overriding signal to make sure that an exception before such instructions-which-reach-forward-in-the-pipeline? | 23:13 |
| @juliusb | i mean something to make sure the exception overrides | 23:14 |
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