| @stekern | juliusb: I'm not seeing you doing anything special for get_gpr in espresso? | 04:32 |
|---|---|---|
| @stekern | I also see that the trace actually snooping the rf_result, but again, espresso isn't doing anything special | 06:58 |
| @stekern | no worries though, I'll figure that out | 06:59 |
| @stekern | think I've got the get_gpr working so the l.nop reports work | 06:59 |
| @juliusb | stekern: I thought I did do something with both espresso and prontoespresso for get_gpr?! I'll check... | 11:56 |
| @juliusb | btw, you're up _early_! | 11:56 |
| @stekern | isn't 4:00 a normal time to start your day with a bit of mor1kx pipeline hacking? :) | 12:37 |
| @stekern | I've got lsu rf bypass working, but hooking up rfa_o and rfb_o straight to lsu_result_o made a terrible path :( | 12:40 |
| @juliusb | stekern: I wish!! | 12:40 |
| @juliusb | oh, really? A path in from the data bus? | 12:40 |
| @juliusb | that's a shame | 12:40 |
| @stekern | I've got that covered by the fact that the loads are stalled one extra cycle the way things are at the moment | 12:41 |
| @stekern | so I forge on, have to get back to that later | 12:41 |
| @stekern | latest synthesis result landed on 90 MHz | 12:41 |
| @stekern | but that might decrease while fixing stuff :) | 12:41 |
| @stekern | I guess I can just stall one extra cycle on the "corner case" where the loaded register are used right after the load | 12:42 |
| @stekern | right now I'm reworking the spr access | 12:42 |
| @stekern | so it will be handled in mem stage | 12:43 |
| @stekern | i.e. address calculated in execute, result shows up in mem stage, and result is written to reg in wb | 12:44 |
| @stekern | -> 1 cycle mfspr | 12:44 |
| @juliusb | all sounds good man | 13:59 |
| @juliusb | stekern: it turns out that I am going to come along to OSHUG tonight | 14:00 |
| @juliusb | whoops | 14:00 |
| @juliusb | I meant that for | 14:00 |
| @juliusb | jeremybennett: it turns out that I am going to come along to OSHUG tonight | 14:00 |
| @juliusb | I'll be a little late though, getting in just after 7 | 14:00 |
| @stekern | juliusb: sorry, the "rf snooping" commit was in your latest commits, I thought I had pulled them | 16:19 |
| @stekern | so that's basically what I do now, except it's a bit more complicated, since the gpr writeback can be in execute, ctrl (mem) or wb | 16:21 |
| @stekern | juliusb: spr access question: the ack logic isn't really implemented, right? | 16:31 |
| @stekern | except for du | 16:32 |
| @juliusb | stekern: SPR Ack logic? | 18:23 |
| @juliusb | like, the ACK for the SPR accesses? | 18:23 |
| @juliusb | the TT and PIC are tied to 1, I can tell you that much :) | 18:23 |
| @juliusb | but the idea is the SPR unit may not ack immediately | 18:23 |
| @juliusb | they may not all be single cycle access | 18:23 |
| @juliusb | so is there a thing in git where if you check out a remote branch and then work on it without branching it locally, and then go branch -a it will says (no branch)? | 20:28 |
| @stekern | juliusb: all are tied to 1, if they wouldn't be reading them wouldn't work (at least not in cappuccino), since the ack is not read anywhere | 20:44 |
| @stekern | it's fine though, I'm thinking about threating them as any 'alu-instruction' | 20:46 |
| @stekern | well, not exactly, it's gonna stall from ctrl/mem stage if ack isnt asserted | 20:53 |
| @stekern | for now I'll just continue to assume that ack is tied to 1 though | 20:54 |
| @stekern | re the git thing, not quite sure what you are after? | 20:56 |
| * ams waves. | 23:38 | |
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