| -!- Jia` is now known as Jia | 05:34 | |
| jeremybennett | stekern: I have updated the OpenRISC Wikipedia page to refer to the LLVM work. If you have a reference to where people can find that work, could you add it (http://en.wikipedia.org/wiki/OpenRISC). | 13:04 |
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| stekern | jeremybennett: nice! I have actually started to document the work a couple of days ago on: http://opencores.org/or1k/LLVM | 13:10 |
| jeremybennett | stekern: That's great and very clear. I wonder if you ought to name the page "OpenRISC LLVM", given there are other processors on OpenCores? I've added some text in the opening paragraph to make it clear this is about OpenRISC. | 13:28 |
| jeremybennett | Added to Wikipedia | 13:31 |
| stekern | yeah, your change good. Although I don't think the other processors on opencores should write about their (possible) LLVM backends on the or1k wiki ;) | 13:46 |
| stekern | s/change/change is | 13:46 |
| stekern | that wikipage is a WIP anyway, I'll write up some more info soon | 13:48 |
| deowen | hey there, I'm hoping I can get a quesiton answered regarding the openrisc jtag debugger, if there's someone knowledgable on the channel | 17:34 |
| juliusb | sure, what's the question? | 18:50 |
| deowen | mainly that that debugger is the only possible one to use for the OR debug interface | 19:24 |
| deowen | I'm running a Xilinx ml501 board | 19:25 |
| stekern | hmm, my llvm-built uclibc+busybox throws "Unknown signal"s at me... | 19:34 |
| juliusb | deowen: ok, what's the issue? I did that port | 20:04 |
| juliusb | and got the debugger working | 20:04 |
| jeremybennett | juliusb: Are you going to this week's OSHUG? | 20:59 |
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