| derRichard | jonibo: ping | 00:54 |
|---|---|---|
| derRichard | i think i've found a serious vm bug in linux openrisc. | 00:54 |
| Lampus|2 | Hello. | 12:49 |
| Lampus|2 | It's again me with my problems =) | 12:49 |
| Lampus|2 | stekern: Sorry for disturbing you again, but I'm need some help. Can you look at this log of adv_jtag_debug http://pastebin.com/mHgDgT0f , please? | 12:57 |
| Lampus|2 | Now I'm using LEGACY_DBG_IF with GENERIC_JTAG_TAP | 12:57 |
| Lampus|2 | adv_jtag_bridge was recompiled with SUPPORT_LEGACY=true | 12:58 |
| Lampus|2 | Why it can't find DEBUG command? | 12:59 |
| Lampus|2 | Exteranal Altera USB Blaster is used | 13:00 |
| stekern | hooked up to what? | 13:00 |
| stekern | some gpios of the fpga? | 13:00 |
| Lampus|2 | Yes | 13:00 |
| stekern | is that known to work? | 13:01 |
| Lampus|2 | Yes, I have used this pins before for some debug signals output | 13:01 |
| Lampus|2 | But adv_jtag_bridge correctly recognize ID Code | 13:02 |
| stekern | I meant, is it known to work with adv_jtag_bridge, LEGACY_DBG_IF and GENERIC_JTAG_TAP? | 13:02 |
| Lampus|2 | Hmmm | 13:03 |
| stekern | and are you using the "legacy" debug if in the fpga? | 13:04 |
| Lampus|2 | stekern: But you have used GENERIC_JTAG_TAP with LEGACY_DBG_IF for de0-nano. What I can use instead? | 13:05 |
| Lampus|2 | Yes, In fpga legacy debug is enabled | 13:05 |
| Lampus|2 | *instead adv_jtag_bridge i mean | 13:06 |
| stekern | I have used it with a ftdi based external debugger and or_debug_proxy and openocd | 13:23 |
| stekern | I'm not saying that your setup shouldn't work though | 13:24 |
| Lampus|2 | Thank you for direction | 13:24 |
| stekern | openocd should have support for usb-blaster afaik | 13:24 |
| Lampus|2 | It works fine with adv_jtag_if and altera_jtag_tap, but only with disabled CRC checking in adv_jtag_bridge | 13:26 |
| Lampus|2 | And breakpoints don't works properly with such configuration | 13:27 |
| Lampus|2 | stekern: And one more question. In what state should be my port for DE0 for merging in upstream? | 13:28 |
| stekern | I'd say it should pass the make rtl-tests simulation and tested on the FPGA | 13:31 |
| Lampus|2 | About tests... For some reasons make rtl-tests for de0-nano need vlib from MultiSim | 13:32 |
| Lampus|2 | But as I know it must works properly with iverilog (Icarus Verilog) too | 13:33 |
| Lampus|2 | One second... | 13:34 |
| stekern | well, if you get it to run with icarus, that's great | 13:35 |
| Lampus|2 | make[2]: Leaving directory `/home/lampus/Projects/FPGA/orpsoc/sw/tests/or1200/sim' | 13:35 |
| Lampus|2 | /bin/sh: vlib: command not found | 13:35 |
| Lampus|2 | make rtl-tests from orpsoc/sim/run directory works fine with iverilog | 13:36 |
| stekern | yes | 13:37 |
| derRichard | jonibo: sorry about the mailinglist confusion. joe and i had a discussion about moderated lists and i thought [email protected] is a black hole | 23:09 |
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